foreword
In order to prepare for school recruitment (for personal use), the blogger sorted out the experience of digital IC front-end (design && verification) && FPGA in previous years. The information comes from but not limited to digital IC workers, FPGA explorers, Moyu Paradigm, CSDN, Niuke.com, blog garden and other public accounts and websites, as well as the blogger’s personal interview experience.
There are many sources of content, and I did not apply for authorization one by one. The source is attached at the end, and the infringement will be deleted. It is only for learning and exchange~
Updating content...(6.28)
It is better to eat with written test questions and hand-torn code
Digital IC written test questions---thousands of questions, with a large amount of control, full of pictures and texts
Table of contents
overall recall summary
Written test summary: I have participated in some written tests, and list the test sites that I have seen twice or more this year.
① Many large companies take more complicated exams, such as ZTE, which has text comprehension, numerical reasoning, and logical reasoning. These are basic skills, for details, please refer to the row test questions. There is also the personality test, which can be answered according to one's own nature, don't be too clever, there will be many repeated questions; ②The advantages and disadvantages of synchronous reset and asynchronous reset; ③Sequence analysis, calculation of establishment and hold time, almost 80% of the front-end design written test questions will test this type of question. It is recommended to look for information and study, it is best to be able to analyze different situations such as BC-WC and OCV. Establishing hold time must be the top priority; ④ frequency division circuit and corresponding Verilog code. Generally speaking, the company will not continue to ask questions after getting an odd frequency division. Of course, it would be better if you can divide by half-integer or any decimal; ⑤ I2C bus protocol. ⑥ The definition, difference, and circuit of classic blocking and non-blocking assignment; ⑦ The design principle of asynchronous FIFO, simple code;
Interview summary:
① Explain your project logically to the interviewer. During the interview, you will find that the interviewer generally does not understand what your project does. One is because the interviewer does not understand your project, and the other is that your logic is not very clear. It is suggested here that when talking about your own project, you should talk about it in terms of modules and functions. Just like when you write code, there is a top module, and the top module will call the module of the next layer. If you speak clearly, the interviewer will be more likely to think that you have done well and that you have good logical expression skills; ② You must know the things on your resume. Proficiency and understanding are different. The interviewer will know what level you are in by just asking a few questions. The same is true for the project, you must be able to speak out when you write it; ③ prepare for self-introduction. This self-introduction does not need to be well prepared, but it should not be too long. The time for self-introduction is mainly for the interviewer to use this time to read your resume, and generally not listen to it; ④ At the end of the interview, the interviewer will ask you if you have any questions, you can prepare in advance.
1. Pingtou brother
Brother Pingtou: ① 30 minutes to ask about the project; ② 15 minutes to check the code sequence by hand tearing; ③ 15 minutes to find the first "1" in the sequence by tearing the code by hand; a total of one hour.
Pingtou brother two sides: ①Ask the project: the difficulties encountered in the project, project innovation points, division of labor, how to solve the problem && why you do it.
2.zeku
Zeku side: ① Ask about the project: project details, structural block diagram && data flow && control flow; ② Stereotype: fifo structure, asynchronous processing (recovery time, removal time), low power consumption design.
Two sides of zeku: 20 minutes, introduce the project.
There are three sides to zeku: the hr side, asking about personality shortcomings, work intentions, etc.
3. Goodix Technology
Goodix Technology: ① What should I do if the chip has been produced and the setup time or hold time is found to be in violation? Can it be remedied? ② What is a synchronous clock and what is an asynchronous clock? ③ Why is the general design synchronous? What are the pros and cons of synchronous and asynchronous circuits? ④ For the resume, ask simple questions about each point covered, and introduce the background significance and innovation points of all projects; ⑤ What are the low-power technologies? ⑥ How is the script written? Are you familiar with python? ⑦ If there is a burst of burst data, how to convert it into a stable data flow? (FIFO) ⑧ What do you think are your strengths and highlights?
Two sides of Goodix Technology: HR side, ①Introduction of family situation; ②Choice of work place; ③Introduction of a project, division of labor and teamwork; ④Planning for one’s own life; ⑤What are the main factors considered in choosing a company;
Three aspects of Goodix Technology: supervisor interview, ① self-introduction; ② project introduction, how to solve the problems encountered in the project? ③ Introduce personal career planning, whether you want to do design or comprehensive/DFT/backend; ④ Understanding of Goodix Technology and the ranking of domestic IC companies.
Goodix: ① Explain your project clearly so that the interviewer can understand it; ② You are given ten days for a project, how to plan your time; ③ What is the method for a single-bit signal from the slow clock domain to the fast clock domain; ④ Why two beats can handle the metastable state; (Non-class)
Goodix: ① Introduce the project; ② Write SPI in the resume, and ask how many working modes SPI has; ③ How to implement cross-clock domain design in the project (asynchronous FIFO); ③ Introduce the principle of asynchronous FIFO and how to implement cross-clock domain internally; ④ The project uses FIFO, ask about FIFO depth; The method of the clock domain; ⑧ how perl reads files, how to operate, and how to process some log results of the simulation (catching ERROR, etc.).
Goodix: ① Ask about the project, device direction, pressure sensor; ② Cross-clock domain processing; ③ The difference between AHB and AXI; ④ How to solve the difficulties encountered in the project; ⑤ Why looking for a job across majors;
Goodix Technology side: ① Ask about projects (SPI timing, IIC timing), ping-pong operation, CPU internal structure, how to control different instruction data paths; ② How do single-bit signals cross clock domains, and how do multi-bit signals cross clock domains; , if a sentence if(a) q<=d; is added to verilog, something will be synthesized.
The second face of Goodix Technology: HR face, ① Introduce your family situation; ② Introduce your hobbies; ③ Intended work location; ④ How many offers you have in hand.
Three aspects of Goodix Technology: supervisor interview, ① English interview in the first 15 minutes, self-introduction in English, English summary project; ② Chinese interview in the last 15 minutes, what is the difference between ASIC and digital chip design? ③ If you have a simulation project, ask questions to compare PLL and ring oscillators, and compare the pros and cons; ④ If you have a PCB project, ask about the difference between PCB and ASIC; ⑤ Does SPI support 1-to-many;
On the technical side, Goodix: ① Why do we need to solve the metastable state, what harm does the metastable state have, and give examples; ② Asynchronous FIFO structure; ③ Understanding of the AXI bus; ④ Understanding of hold violation;
Two sides of Goodix Technology: HR side, ① self-introduction; ② teamwork, with examples; ③ things that have frustrated me so far; ④ which offers you got and how you think about them.
Goodix Technology has three aspects: the manager’s aspect, ①self-introduction; ②combined with things to talk about your own advantages; ③personal career planning; ④do you want to be a system architect, or are you proficient in unilateral aspects; ⑤your views on some of the companies you submitted.
Goodix interview memories: ① The city you want to work in, why you chose this city; ② Self-introduction; ③ Introduce the project; ④ Sampling law, oversampling, oversampling can ensure that the signal after sampling is not distorted, and achieve a good signal-to-noise ratio, which is generally used in sigma-delta DAC or ADC; ⑤ What is the impact of increasing the sampling frequency? (The sampling frequency is doubled, and the signal-to-noise ratio is doubled by the square root); ⑥ How to test the stability of high-speed interfaces; ⑦ How to write timing constraint files; 11. How is division done? What if it is divided by an odd number? 12. What methods are available across clock domains. 13. Introduce asynchronous FIFO; 14. What are the types of coverage; 15. What are the differences between different FPGA banks? (level characteristics and electrical physical characteristics) 16.a is signed 5bit data, b is signed data, assign -a to b, how to do it? 17. How to do b=a^3+a^2*2a? (lookup table or multiplier)
Goodix Technology FPGA job interview memories: The project questions are very deep, and the basic knowledge questions are extended. ① The maximum rate of the FPGA IO bank used; ② The voltage amplitude between LVDS differential signals; ③ Project data throughput; ④ The bit width of the embedded multiplier at the bottom layer; How do you plan to do it; ⑩ how is the io constraint determined; 11. The control pin of the protocol; 12. The maximum rate of data transmission; 13. How many logic resources are occupied by the project; 15. How to transplant the gated clock to FPGA; 16. The difference between ASIC design and FPGA design at the RTL level; 17. The FIFO data bit width && depth used; 18. Measurement principle, equal precision measurement principle, how to analyze error analysis, and which parameters will affect the accuracy.
Goodix's FPGA is basically communication and prototype verification. It is difficult to get an interview opportunity if there is no relevant project in the resume. The interview is standard with two interviewers for communication + prototype verification.
Position: Digital IC Design
Goodix Technology side: ① self-introduction; ② school courses and grades; ③ project introduction; ④ python mastery;
Two sides of Goodix Technology: ① self-introduction; ② project introduction; ③ understanding of family situation; ④ do you have a partner;
Three aspects of Goodix Technology: ① self-introduction; ② what courses, grades, and professional rankings during school; ③ project introduction; ④ personal career planning; ⑤ evaluation of personal strengths and weaknesses;
4. MediaTek
Position: Digital IC Design, Hefei
MediaTek side: ① Self-introduction; ② Choose one of the best projects and introduce in detail; ③ Apply for an IC job, the competition is fierce, what are your advantages; ④ Introduce the process of IC design; ⑤ Write a good verilog program;
Two sides of MediaTek: ① Which of the three projects in your resume has the greatest impact on you and which one you are most familiar with; ② How is the time allocated in the project; ③ Do you understand the steps of the entire digital logic structure design; Which; ⑩ How do you feel about Anhui; 11. Family situation; 12. Personality traits.
MediaTek: On July 8, 2022, the interview time is 46 minutes. ① Self-introduction; ② Talk about the project, frame diagram (code amount), how to build tb, how to see whether the function is realized; ③ axi, apb, ahb basic characteristics, application scenarios; draw the timing diagram of apb's sending data; what is the default value of preready signal; ⑤ Is the constant phase difference of different frequencies synchronous or asynchronous? Why? ⑥ Do you know anything about synthesis? ⑦ How is the competition divided? What unforgettable experience did you have during the completion process? ⑧ Have you ever studied digital filtering? ⑨ How did you solve the difficulties you encountered from undergraduate to graduate? ⑩ What is your impression of MediaTek? 11. What do you want to ask?
The second side of MediaTek: July 25, 2022, the interview time is 15 minutes. ① Self-introduction; ② What does your teaching and research section do? Is the final project in this project a real thing? ③ Do you have any other studies besides the project on your resume? ④ Why not consider a Ph.D.; ⑤ Why do you want to come to the IC industry; ⑥ Have you learned some open source codes?
Three sides of MediaTek: August 3, 2022, the interview time is 15 minutes. ① What does the msi001 chip achieve? ② How is demodulation realized; ③ How is iq signal realized; ④ Why do you need a guide; ⑤ What is your personality; ⑥ What kind of company do you want to join; ⑦ Future planning;
5. Nova Technology
Nova side: ① Self-introduction; ② Introduce the project, and ask questions about AXI, asynchronous FIFO, SDRAM, and Serdes; ③ What kind of situation is suitable for using SVA (because I said I have written AXI assertions); ④ Have you ever written a state machine? What are the advantages of using a state machine? Which situations are suitable for using a state machine; ⑤ Do you understand synthesis? Talk about the constraints during synthesis; ⑥ What debugging methods have you used; ⑦ What do you think is the most fulfilling thing;
6. Chichuang North
Position: Digital chip design engineer
Chipone’s northern side: ① Self-introduction; ② Introduce the resume project and ask about resume details; ③ You said you know UVM, what is UVM; ④ You wrote a verification project in your resume, what language is the reference model in the project written in? How to simulate FIFO behavior? ⑤ The resume writes that the project function coverage rate is 100%, which seems to have given a lot of incentives. What incentives did you give? How did you give it? ⑥ How did you collect the functional coverage? How was it merged? ⑦ You said you used the register model, and tell us about your understanding of the register model. When is it better to use the front door for access and when is it better to use the back door for access? ⑧ Do you know the phase mechanism? Why introduce the phase mechanism? ⑨ Are you familiar with sv, what is the difference between fork-join, fork-join_any, fork-join_any? ⑩ You said you know perl, what is @ARGV? How to pass parameters to the program through @ARGB? $! Do you understand? 11. Are you familiar with verilog? Name the characteristics of three verilog codes. 12. Are you familiar with DC synthesis? === Is it possible to synthesize? 13. Ask rhetorically.
Personal summary: Basically ask questions according to the resume, and the content of the resume must be clear.
7. Huawei
Position: Huawei Logic Design
Huawei: ① What parameters should be paid attention to in chip selection; ② What software is used for simulation; ③ Do you understand the verification method? Do you know how to increase coverage? ④ Problems encountered in FPGA development; ⑤ What are the low power consumption methods; ⑥ How do glitches come from;
8. DJI
Position: chip development
DJI side: PR project: ① Introduce the basic parameters of the chip; ② Introduce in detail the whole process, what difficulties encountered, and how to solve them; ③ How floorplan works and why; ④ How to make adjustments before the route to avoid short after the route; ⑤ What is the scripting ability; ⑥ How many lines of code have been written in the project; ⑦ How does the shell achieve keyword capture; ⑧ How does tcl achieve keyword capture; ⑨ How does python achieve keyword capture;
Two sides of DJI: 25 minutes, ① Self-introduction; ② Project questions; ③ Do you know about DJI chips, please introduce; ④ If Huawei, Cambrian, Nvidia, and DJI all give you an offer, which one would you choose and why; ⑤ What are the benefits of choosing a product company compared to a pure chip company.
9. Allwinner Technology
Position: Digital IC Design
Quanzhi side: ① The clock domain of A is 100MHZ, and the clock domain of B is 10MHZ. In the asynchronous FIFO, because the slow clock domain collects the pointer of the fast clock domain, is there a problem with the gray code changes collected by B? ② Fast to slow transmission pulse; ③ a, b, c, d, find the sum of the second largest and third largest --- min(max(a,b), max(c,d)) + max(min(a,b), min(c,d)); ④ Regarding Quanzhi's opinion, have you received other offers?
Quanzhi’s two sides: HR, ① whether it is the postgraduate entrance examination or the postgraduate entrance examination, why the postgraduate entrance examination failed; ② how to solve the relatively large setbacks; No prize. ⑩ Is there anything done after the time node?
10.OPPO
Position: chip design
On the OPPO side: ① Introduce the internship process and project; ② Introduction to the FPGA image project and the overall process; ③ The implementation process of a specific algorithm; ④ How many resources are used; ⑤ Which software tools have been used;
Batch in advance. Position: chip design
OPPO side: ① What is the FPGA back-end process; ⑨ Approximate amount of code for several of your projects, or roughly how many equivalent gates; ⑩ The concept of setup/hold, how to solve violations and why; 11. How DE and DV work together; 12. Synchronous reset and asynchronous reset, and their respective advantages and disadvantages; 16. Asynchronous FIFO, Gray code to judge the condition of pointer empty and full, what processing is required for Gray code cross-clock domain transmission, why use Gray code; 17. Introduce the internship experience, how to coordinate the team's cooperation; 18. How to realize odd frequency division, even frequency division and decimal frequency division, just talk about ideas; Cross clock domain design, asynchronous FIFO. 20. Do you know the difference between AXI and AHB, and what are the advantages and disadvantages of each; 21. What to do if the timing of FPGA is violated; 22. Have you understood the power consumption? How do static power consumption and dynamic power consumption come from, and how to achieve low power consumption; 23. Have you ever studied signal processing courses, and what advantages does FFT have over DFT? 24. How to reduce dynamic power consumption?
Two sides of OPPO: 30 minutes, ① Self-introduction; ② Introduce the project, briefly introduce the algorithm of your project and some goals that this algorithm can achieve; ③ Your future career planning; ④ How do you think about your self-learning ability; ⑤ How do you think about team work; ⑧ Rhetorical questions.
OPPO side: missing
Two sides of OPPO: ① Introduce the project architecture; ② What to do if the chip data transmission rate is different from the working rate; ③ Do you want to be a front-end, architecture or back-end; 11. Introduce the difference between write back and write through; 12. Hand-tear the code for three-way frequency, and ask what can be improved for three-way frequency; 13. Do you know DFT related knowledge; 14. How do you think about working time and place.
advance batch
OPPO side: ① self-introduction; ② project introduction; ③ the difference between AXI AHB and APB, why the writing channel of AXI is independent, can AHB read and write at the same time; ④ advantages and disadvantages of pipeline design;
Two sides of OPPO: ①Introduce the project; ②How to verify the correctness of functions; ③Explain the VCS and FPGA verification process; ④How to do stress testing in verification, how to do many cases; ⑤Design or verification; ⑥Chat.
11. GigaDevice Innovations
Position: storage design post
GigaDevice's innovative side: As soon as the interviewer came up, he asked to draw a gate D flip-flop and explain the working principle. Reviewed the written test questions. Let's analyze the cause of the metastable state from the perspective of the gate circuit. Let draw a setup time, hold time waveform diagram, and mark the delay of each part in the diagram. In the rhetorical question section, the interviewer said that the storage design department in Xi'an has relatively few verilog writers, and the requirement for engineers is to understand the underlying circuit.
Two sides of GigaDevice innovation: HR side, comprehensive questions, why choose GigaDevice, etc. Finally, at the beginning of October, Zhaoyi HR called to say that I was admitted and confirmed my job intention. Because according to the description of one interviewer, I was worried that the direction to go in was too narrow and did not match, so I chose to refuse.
12. Ziguang Guoxin
Position: ASIC design post
Unisplendour National Chip: The interviewer already knew my project very well, and asked some knowledge about RISC-V processors, and the difference between APB, AHB, and AXI in the AMBA protocol. Talk about the IC design process, how much you know about ASIC, etc. The interview time is about half an hour.
Ziguang National Chip two sides: HR side, the interviewer is approachable, and talked about the experience of one side and some comprehensive questions. Chatted for 40 minutes. Received letter of intent and offer in late September.
13. BYD
Position: Digital IC design engineer (offered)
There are three rounds of interviews by submitting your resume through school recruitment. The first is the HR interview, which is about understanding the basic information; the second is the technical interview, where the interviewer has personnel from the HR and technical departments and asks a lot of technical questions; the third interview is where the department head of your department talks to you about the salary and the entry process.
BYD interview memories: ① Self-introduction; ② Introduce the project; ③ Briefly describe the composition of pmos, what is the difference between the enhanced type and the depletion type; ④ What is the setup time and hold time;
14. Guodian NARI
Position: Digital IC Design Engineer
Guodian Nanrui side: 40 minutes. ① Self-introduction; ② What are your grades in school and what courses you have studied; ③ What projects you have participated in, and questions about project details; ④ FPGA structure description; ⑤ What is asynchronous reset; ⑥ Frequency division circuit;
15. Haiguang Information
Position: Digital IC Design Engineer
Haiguang side: ①Self-introduction; ②Courses and grades; ③Project introduction; ④Simplification of logical expressions; ⑤Differences between flash, cache, DRAM, and SDRAM;
16. Innosilicon
Position: Digital IC design engineer (offered)
Innosilicon side: telephone interview, 54 minutes. ① Asked some questions in the written test; ② Asked all three items written on the resume; ③ soc architecture, AXI bus content (outstanding); ④ Reverse question (what direction does Innosilicon have? Reply: There are some controller IP designs of GPU, PCIE, and DDR to make a large SOC)
Innosilicon two sides: telephone interview, 33 minutes. ① Asked all the items on the resume. The interviewer also knew about radio frequency, and asked how the baseband signal was converted to radio frequency, and whether it was IQ modulation; ② How is DDR integrated into the project? I said block design, and he said that it can be integrated with RTL, which will be better simulated; ⑤ The workflow of VCS, what files are generated after compile; ⑥ Ask back.
Position: Digital IC design engineer (offered)
Innosilicon side: Telephone interview, 30 minutes. ① Question item: How to synchronize the clock? How to calculate prop_delay; ② How is the clock corrected? Is it necessary to correct the real local clock? ③ Do you know AMBA? Answer to understand AHB and APB, and ask, do not understand AXI? Answer, I don’t know; ④ What are the implementation methods of the arbitrator, answer fixed priority and round-robin arbitration; ⑤ The method of crossing clock domains; ⑥ How to set timing constraints; ⑦ How to do timing optimization;
Innosilicon two sides: telephone interview, 1 hour. ① describes a cross-clock domain scenario. From 3M to 20M across clock domains, without handshake or asynchronous fifo, to transmit 8bit data (3M clock changes data once per clock), what should I do? ② Asynchronous reset and synchronous release, is it possible for the second flip-flop to appear metastable when it is released? ③ From the A clock domain to the B clock domain, use the usual two beats for synchronization. What conditions must the clock cycles of these two clock domains meet? That is to say, what conditions can be met to make two shots? Timing constraints and timing optimization; ⑤ Ask questions about inputdelay and output delay, which part does inputdelay belong to? What is the impact on FPAG? ⑥ Ask the cross-clock domain in the project. ⑦ I asked about my understanding of PCIE, and I said that I understand PCIE, and I read a book on PCIE architecture; ⑧ VCS-related questions; ⑨ What advantages do you have, let the interviewer admit you; ⑩ Why go to Xi’an; 11. Reverse question: How is the training mechanism? Answer: The tutor is 1 on 1, and asks: When will the result come out? Answer: Results will be available in one to two days. Then I made an offer that night.
Small suggestion: Innosilicon is more interested in everyone's written test results, so everyone should take the written test seriously and prepare in advance!
17. AMD
Position: Digital IC Design Engineer
On the AMD side: ① Self-introduction; ② What are the courses, grades, and professional rankings during school; ③ Project introduction; ④ Chip packaging; ⑤ The structure of NMOS and PMOS;
Position: Digital IC Design Engineer
On the AMD side: ① self-introduction; ② courses and grades; ③ project introduction; ④ how is your English level; ⑤ the difference between synchronous reset and asynchronous reset; ⑥ the difference between sequential logic and combinational logic;