Digital IC design study notes _8-bit 7-segment digital tube 2

Digital IC design study notes

8-digit 7-segment digital tube 2

1 原理图
2 Verilog 代码
3 Modelsim仿真

1. Schematic

• Because the module on the AC620 development board does not support direct drive of the digital tube, it is necessary to connect two 74HC595 modules to convert the serial data into parallel data for the digital tube; and HC595_driver is used to output the original design (HEX8) The signal is converted into a signal suitable for HC595, DS, SHCP, STCP;

(1). The overall schematic diagram of the system

(2). Timing diagram of 74HC595

(3). HC595_driver timing diagram

2 Verilog code

module hc595_driver#(
	parameter CNT_MAX = 2
)
(
	input clk, //50MHz = 20ns
	input rst_n,
	input en,
	input [15:0] data1,
	
	output reg DS,
	output reg SHCP, //12.5MHz, 80ns=1:40ns+0:40ns
	output reg STCP//latch
);
	reg [7:0] div_cnt; //freq divid counter
	reg [5:0] flag_cnt;
	wire sck_flag;
	reg [15:0] data_reg;
	
//----en--------------------------------------
	always@(posedge clk)
		if(en)	
			data_reg <= data1;
		else
			data_reg <= data_reg;
//----div_cnt---------------------------------
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			div_cnt <= 0;
		else if(div_cnt == CNT_MAX-1)
			div_cnt <= 0;
		else
			div_cnt <= div_cnt + 1'd1;

	assign sck_flag = (div_cnt == CNT_MAX-1'd1)? 1'd1:1'd0;

//----flag_cnt---------------------------------
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			flag_cnt <= 0;
		else if(sck_flag) begin
			if (flag_cnt == 32)
				flag_cnt <= 0;
			else
			flag_cnt <= flag_cnt + 1'd1;
			end
		else
			flag_cnt <= flag_cnt;

//----STCP(latch)-DS--SHCP---------------------------
	always@(posedge clk or negedge rst_n)
		if(!rst_n)begin
			STCP <= 0;
			DS <= 0;
			SHCP <= 0;
		end
		else begin
			case(flag_cnt)
			0: begin
					SHCP <= 0;
					DS <= data_reg[15];
					STCP <= 0;
				end
			1: begin
					SHCP <= 1;
					DS <= data_reg[15];
					STCP <= STCP;
				end
			2: begin
					SHCP <= 0;
					DS <= data_reg[14];
					STCP <= STCP;
				end
			3: begin
					SHCP <= 1;
					DS <= data_reg[14];
					STCP <= STCP;
				end
			4: begin
					SHCP <= 0;
					DS <= data_reg[13];
					STCP <= STCP;
				end	
			5: begin
					SHCP <= 1;
					DS <= data_reg[13];
					STCP <= STCP;
				end
			6: begin
					SHCP <= 0;
					DS <= data_reg[12];
					STCP <= STCP;
				end	
			7: begin
					SHCP <= 1;
					DS <= data_reg[12];
					STCP <= STCP;
				end
			8: begin
					SHCP <= 0;
					DS <= data_reg[11];
					STCP <= STCP;
				end	
			9: begin
					SHCP <= 1;
					DS <= data_reg[11];
					STCP <= STCP;
				end
			10: begin
					SHCP <= 0;
					DS <= data_reg[10];
					STCP <= STCP;
				end	
			11: begin
					SHCP <= 1;
					DS <= data_reg[10];
					STCP <= STCP;
				end
			12: begin
					SHCP <= 0;
					DS <= data_reg[9];
					STCP <= STCP;
				end	
			13: begin
					SHCP <= 1;
					DS <= data_reg[9];
					STCP <= STCP;
				end
			14: begin
					SHCP <= 0;
					DS <= data_reg[8];
					STCP <= STCP;
				end	
			15: begin
					SHCP <= 1;
					DS <= data_reg[8];
					STCP <= STCP;
				end
			16: begin
					SHCP <= 0;
					DS <= data_reg[7];
					STCP <= STCP;
				end	
			17: begin
					SHCP <= 1;
					DS <= data_reg[7];
					STCP <= STCP;
				end
			18: begin
					SHCP <= 0;
					DS <= data_reg[6];
					STCP <= STCP;
				end
			19: begin
					SHCP <= 1;
					DS <= data_reg[6];
					STCP <= STCP;
				end
			20: begin
					SHCP <= 0;
					DS <= data_reg[5];
					STCP <= STCP;
				end
			21: begin
					SHCP <= 1;
					DS <= data_reg[5];
					STCP <= STCP;
				end
			22: begin
					SHCP <= 0;
					DS <= data_reg[4];
					STCP <= STCP;
				end
			23: begin
					SHCP <= 1;
					DS <= data_reg[4];
					STCP <= STCP;
				end
			24: begin
					SHCP <= 0;
					DS <= data_reg[3];
					STCP <= STCP;
				end
			25: begin
					SHCP <= 1;
					DS <= data_reg[3];
					STCP <= STCP;
				end
			26: begin
					SHCP <= 0;
					DS <= data_reg[2];
					STCP <= STCP;
				end
			27: begin
					SHCP <= 1;
					DS <= data_reg[2];
					STCP <= STCP;
				end
			28: begin
					SHCP <= 0;
					DS <= data_reg[1];
					STCP <= STCP;
				end
			29: begin
					SHCP <= 1;
					DS <= data_reg[1];
					STCP <= STCP;
				end
			30: begin
					SHCP <= 0;
					DS <= data_reg[0];
					STCP <= STCP;
				end
			31: begin
					SHCP <= 1;
					DS <= data_reg[0];
					STCP <= STCP;
				end
			32: begin
					STCP <= 1;
				end				
				default: begin
					SHCP <= 0;
					DS <= 1'b0;
					STCP <= 0;
				end
			endcase
		end
		
endmodule

	
endmodule
//-------------------------------------------------
//----testbench--------------------------------
`timescale 1ns/1ns
`define clock_period 20
module hc595_driver_tb;
	reg clk;
	reg rst_n;
	reg [15:0] data;
	reg en;
	
	wire DS;
	wire SHCP;
	wire STCP;

hc595_driver uut(
	.clk(clk), //50MHz = 20ns
	.rst_n(rst_n),
	.en(en),
	.data1(data),
	
	.DS(DS),
	.SHCP(SHCP), //12.5MHz, 80ns=1:40ns+0:40ns
	.STCP(STCP)//latch
);
	initial clk = 1;
	always #(`clock_period/2) clk = ~clk;
	
	initial begin
		rst_n = 0;
		en = 0;
		data = 16'h9876;
		#1000;
		rst_n = 1;
		#304;
		en = 1;
		#3000;
		en = 0;	
		#20000;
		data = 16'hfedc;
		#3000;
		en = 1;
		#3000;
		en = 0;
		#3000;
		$stop;
		end
endmodule

3. Modelsim simulation

The content is derived from the summary of the self-study notes of Xiaomei FPGA ^^

[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~