Digital IC design study notes
Low power design 1
1. 目的
2. 功耗的分析
2.1 功耗的类型
2.2 按结构分类
2.3 翻转率的计算
3. 低功耗设计方法
3.1 系统与架构级低功耗设计方法
3.2 RTL级低功耗设计方法
3.3 门级电路低功耗设计方法
3.4 物理级低功耗设计方法
1. Purpose
- (1). Demand for portable devices
- (2). Reliability and performance requirements. The
higher the power consumption, the more heat and noise, the more it affects the normal operation of the device and reduces the performance of the device. - (3). Cost The
greater the power consumption, the higher the heat, and the later packaging will increase the heat dissipation equipment, which will increase the cost.
2. Analysis of power consumption
-
2.1 Types of power consumption
1). Dynamic power consumption
(1). Switching power consumption (flip power consumption, main)
The power consumption consumed by charging and discharging the load capacitor.
VDD: power supply voltage
Cload: load capacitance
Tr : switching rate = 2f (rising edge, falling edge)
average power consumption:
(2). Short-circuit power (internal power consumption)
PMOS, NMOS, when simultaneously conducting, between VDD and VSS The short-circuit current formed between the time and the power consumption. Mainly related to the state and path, that is, state dependent path dependent.
VDD: power supply voltage
Qx: the amount of charge from the power supply to the ground in a flip
Tr: flip rate = 2f (rising edge, falling edge)
Summary : Dynamic power consumption is mainly related to the power supply voltage , The inversion rate is related to the load capacitance.
2). Static power consumption The power consumption
caused by the leakage current is mainly related to the process and state, and the power consumption is different under different input states.
The composition of the leakage current :
(1). PN junction reverse current
(2). The sub-threshold current between the source and the drain (sub-threshold current): the gate voltage is less than the turn-on threshold voltage , Resulting in leakage current from the drain to the source of the FET. The narrower the transistor, the greater the leakage current.
(3). Gate induced drain leakage between the gate and the drain
(4). Tunneling current between the gate and the substrate (Gate Tunneling): Add a signal to the gate, between the gate and the substrate Capacitance is generated, and then current is generated, and there is power consumption. This is one of the main current sources after the ultra-nano process.
3). Surge power consumption The power consumption
caused by inrush current is generally not concerned.
Inrush current : The maximum current that the device passes when it is turned on or awakened. -
2.2 Classification by structure
(1). Clock tree power consumption
(2). Processor power consumption
(3). Memory power consumption
(4). Other logic and IP power consumption
(5). Input and output PAD power consumption
-
2.3 Toggle rate calculation (Toggle rate)
concept: unit time, the number of signal flips.
Tr = 4 times/80us = 50000 Hz
Note: Use the report_lib slow -power command in the EDA tool to list the power consumption information in the library.
3. Low-power design method
-
3.1 System and architecture-level low-power design method
System and architecture-level low-power design can save more than 70% of power consumption.
Methods :
① Multi-voltage design technology (Multi-VDD)
(a) Each voltage area has a fixed voltage (fixed)
(b) Each voltage area has a fixed multiple voltage, and the software determines which one (active)
(c) Adaptive The way, each voltage domain is variable, and the software determines which one (dynamic)
② Software and hardware co-design
DVFS technology: dynamic voltage frequency adjustment, dynamic voltage dynamic frequency scaling: reduce the voltage and frequency of different modules to just meet the minimum requirements of the system, Reduce the power consumption of different modules in the system.
③ System clock distribution
Set the system to different working modules and add the clock control module. In different working modes, select clocks with different working frequencies, and close the unused modules.
④ Algorithm and IP selection
Algorithm: Logarithmic system is better than linear system.
IP: achieve the same function, which power consumption is higher.
⑤ Other
methods:
Asynchronous design: no global clock is needed, and handshake signals are used to reduce power consumption.
Cache: Based on the cache system, Reduce power consumption (such as FFT algorithm in DSP, add cache between memory and processor)
DFT: reduce power consumption in design for testability, low power consumption of memory -
3.2 RTL-level low-power design method
① Parallel and pipeline selection
Parallel: reduce the system clock frequency and reduce power consumption.
Pipeline: Insert an M-level pipeline on a long combinatorial logic path, and the path length becomes 1/M, from The discharge capacitance becomes C/M. If the system clock frequency does not change, a lower driving voltage can be used to reduce the overall power consumption.
② Resource sharing and state coding If the
same operation occurs in multiple places, resource sharing can be used to avoid repetition and reduce power consumption.
Data coding adopts state coding with low turnover rate, which can reduce dynamic power consumption. (Gray code instead of binary code)
③ Operand isolation
In a period of time, the data output is useless, you can change the input to a fixed value, so that the data path is not inverted, reducing power consumption.
Note: Increase area will affect DFT
④ Gated clock The
clock tree is composed of a large number of buffers and inverters. The clock signal has the highest rate in the design, and the power consumption of the clock tree can be as high as 40% of the entire design power consumption. The gated clock circuit is added. Reduce the flip of the clock tree and reduce power consumption. At the same time, as the flip of the register clock pin is reduced, the internal power consumption of the register is also reduced. Generally, 20%~60% of the power consumption can be saved. -
3.3 The
concept of gate-level circuit low-power design method : starting from the completion of the gate-level netlist mapping, the design is optimized to meet the design rules and timing.
Optimized power consumption types: design total power consumption, static power consumption, dynamic power consumption
methods : -
① Static power optimization
Multi-threshold voltage design:
size (↑), device supply voltage (↑), threshold voltage Vt (↑), leakage power (↓), gate delay (↑), speed (↓).
Size (↓), device supply voltage (↓), threshold voltage Vt (↓), leakage power consumption (↑), gate delay (↓), speed (↑).
–>>Use cells with low threshold voltage (Lvt) in the critical path, and use cells with high threshold voltage (Hvt) in the non-critical path –>Reduce power consumption -
② Dynamic power consumption optimization based on EDA The
switching behavior of the circuit needs to be provided, and the tool optimizes the power consumption of the entire circuit according to the turnover rate of each node.
Use the compile/physopt command to optimize timing and dynamic power consumption at the same time. -
③ A
certain module in the power gating chip does not work for a period of time, and the power supply that can be turned off (MTcmos switch can be used to turn off the power supply, and the back-end tools add MTCMOS during layout), and the module is in sleep State, the power consumption is very low; when waking up, it is necessary to maintain the state before the power is turned off, and use the retention register to remember the state. -
3.4 Physical-level low-power design method
(1). Nodes with high turnover rate should be routed as low-capacitance metal layers as possible.
(2). The nodes with high turnover rate should be as short as possible.
(3). High-load nodes and buses use low-capacitance metal layers.
(4). Particularly wide devices can be designed with a special layout to reduce drain capacitance.
(5). Some unlimited tools can generate clock trees with power consumption as the target.
—Part of the content comes from learning from other blogs. Thanks^^
https://www.cnblogs.com/IClearner/p/6923585.html
[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~