The complete back-end design consists of two design parts: back-end semi-customization and back-end full customization:
The back-end full-custom design refers to the physical library unit first designed according to the design requirements in the early stage of design. The physical unit library is composed of standard cell library, IP library and customized component units that meet special needs. The physical library is the subsequent back-end Semi-custom designs provide the basis for physical implementation.
Back-end semi-custom design refers to the use of layout and routing tools to complete the layout design of the entire chip based on the standard cell library and IP library completed in the back-end full customization stage. This process is called digital back-end design (automatic layout and routing) -APR).
Digital IC back-end design refers to the process of placing and routing the gate-level netlist generated by the front-end design through EDA design tools, performing physical verification, and finally generating GDSII data for manufacturing. Its main job responsibilities include: chip physical structure analysis, logic analysis, establishment of back-end design process, layout layout and routing, layout editing, layout physical verification, contact foundry and submit production data.
The digital back-end design process is as follows:
The back-end process of digital IC design is shown in the figure above, mainly including the following steps:
1. Logic synthesis is to map the RTL code to a netlist related to the process library, and this process can be implemented on the front end. The entire code compilation process in logic synthesis is carried out under artificially set constraints, and the tools are guided to complete the work of the Compiler through constraints and setting goals. The logic synthesis process can be regarded as a multi-objective (frequency, area, power consumption) multi-constraint engineering optimization problem. The output netlist is mainly used in processes such as P&R.
2. DFT (Design ForTest, Design for Testability) is to add a testable circuit inside the chip, which can expose the internal signal to the outside, and its purpose is to facilitate the test after the chip is taped out. Common DFT techniques include scanning test (SCAN), boundary scan test (BSCAN), built-in self-test (BIST), static current (IDDQ) test, etc. SCAN design is to replace non-scanning units (such as ordinary registers) with scannable units, and then connect them into a scan chain; BSCAN test target is usually IO-PAD, which is often used for board-level and system-level trace debugging; BIST typical application It is a memory test, that is, MBIST.
DFT generally has a dedicated part in charge, and after the DFT design is completed, it will formally enter the back-end design process.
3. Data import. The design data required for the back-end design mainly includes the gate-level netlist generated through synthesis after the front-end design, SDC constraint files with timing constraints and clock definitions, and physical design cell library data.
4. Floorplan. At this stage, the physical layout of the IO Pad and macrocells in the design, the layout constraints of the standard cells, and the implementation of the power network layout are completed. The IO Pad reserves a position in advance, while the macro cells are mainly placed according to the timing requirements. The standard cells define a specific area range and are automatically placed by the tool according to the layout constraint information. The power network layout completes the reasonable power supply network required for chip work. .
5. Unit placement (Placement). After layout planning, the positions of macro cells, IO Pad and the constrained area for placing standard cells have been determined, and the APR tool automatically places standard cells based on netlist and timing constraint information.
6. Clock Tree Synthesis. This stage is used to implement the clock tree in the chip. The clock in the chip needs to drive all the sequential units in the design, and the clock network and the buffers it uses constitute a physical clock tree.
7. Global & Detail Route. Wiring refers to connecting the input and output ports of each unit module with interconnecting wires according to the connection relationship of the circuit under the conditions of satisfying the process rules and the restrictions on the number of wiring layers, line width, line spacing, and electrical performance constraints of reliable insulation of each line network. connect them.
8. Voltage decay analysis (IR-drop&EM). After the wiring is completed, the design data is basically determined, and the power consumption and voltage drop analysis of the entire design will be more accurate. Therefore, the voltage drop analysis is used to evaluate whether the power network meets the design requirements.
9. Timing verification and ECO. The back end generally uses static timing analysis to verify whether the system meets the timing requirements. ECO (Engineering Change Order) is to make small-scale changes to the circuit and unit layout without re-layouting and wiring. Manually modify the layout to meet the functional and timing requirements or fix some bugs, avoiding repeating the design process of the entire chip.
10. Functional equivalence check. The layout and routing process needs to modify the gate-level netlist according to the physical situation, so the equivalence check process is used to confirm whether the final netlist is functionally consistent with the initial netlist provided by the front end.
11. Physical Verification. Physical verification mainly includes DRC and LVS. DRC is to check the design rules of each layer of physical graphics in the chip layout to ensure that the tape-out requirements are met. LVS guarantees that the physical layout produced by the physical verification tape-out is consistent with the actually designed circuit diagram.
12.Signoff, the signoff referred to in the back end refers to the re-inspection of the design data to confirm that the design data meets the delivery standards before the design data is handed over to the chip manufacturer for production. These inspections and confirmations are collectively referred to as signoff. Examples include timing signoff and physical signoff.
13. Tapeout. In the case that all checks and verifications are correct, the final layout GDSII file is passed to the tape-out factory for mask manufacturing.
IC backend design tool introduction:
The tools commonly used in digital back-end design are mainly launched by Cadence, Synopsys and Mentor.
Logic synthesis tools: Synopsys DC, Cadence Genus
Design for testability tools: Mentor series DFT tools, Synopsys DFT Compiler
Placement and routing tools: Cadence Innovus, Synopsys ICC2
Static timing analysis tools: PrimeTime, Encounter Timing System
Power Analysis Tools: RedHawk, PrimeRail, Encounter Power System
Formal verification tools: Formality, Conformal
Parasitic parameter extraction tools: QRC Extraction, Star-RCXT, Caliber xRC
Physical verification tools: Caliber, Hercules