1 Introduction

This blog aims to describe the basic skills necessary for digital chip & FPGA beginners. Students who need it can take it by themselves.

2. Skills

The first is the skills that need to be mastered

● Verilog

It is a kind of hardware description language. It can be used in digital electronic system design, simulation verification, timing analysis, and logic synthesis of digital logic systems. It is currently the most widely used hardware description language.

Verilog HDL

● Fundamentals of digital circuits

● Clock reset design

○ Systemverilog

It is expanded based on Verilog language and introduces object-oriented design technology, which can be designed more flexibly to meet various needs of digital verification.

As a designer, you can have a little understanding of the basic syntax of SV, which can facilitate the writing of TB files.

SystemVerilog HVL: Introduction and content navigation

● Linux

Digital IC is basically designed and verified in the Linux environment, so the basic operation of Linux is essential!

Linux: Directory and file handling commands

Linux: System Operation Commands

Linux: Vim editor

● TCL

A scripting language, which is the interactive command language of most EDA tools, so it has high cross-platform reusability.

Tool Command Language(TCL)

● Compilation and simulation tools VCS & Verdi

Once you have learned the language and framework, you need a software platform for simulation. VCS and Verdi are commonly used simulation compilation tools in the Linux environment.

Compilation and simulation of VCS and waveform viewing of Verdi based on Makefile

○ Compile the simulation tool Questasim

It is a commonly used simulation compilation tool in the Windows environment

Questasim Getting Started Guide

● FPGA development environment Vivado

The most commonly used FPGA development environment, FPGA practitioners must learn

FPGA development environment Vivado

● High-Level Synthesis High-Level Synthesis (HLS)

● Code inspection/cross-clock domain inspection tool Spyglass

● Logic synthesis tool Design Compile (DC)

● Python/C++

In the verification platform built using UVM, the reference model needs to use modules written in C/C++.

C++ basics and STL

For data simulation of algorithms, Python/MATLAB is often used to design reference models.

○ SVN

A version control tool for those who need it.

Detailed explanation of SVN commands under Linux

Detailed Explanation of SVN Common Commands

3. Technical articles

After learning the above basic skills, the next step is to carry out targeted learning according to specific work scenarios and project requirements, including bus interface, technical protocols, etc.

● RTL Design Flow

Includes tips and guidelines for the design process

● RTL Design Spec

The content of the design document can be designed according to the order of the document in the actual design process.

RTL Design Spec

● RTL Project Directory

How the project directory is organized

RTL Project Directory

● RTL Coding Tech

Dos and don'ts and tips when coding

RTL Coding Tech

● RTL algorithm design & timing design

Multiple design examples, including algorithm class, that is, the realization of mathematical algorithms on RTL, and timing class, that is, timing structures such as ping-pong, parallel, and pipeline

RTL Algorithm Design & Timing Design: Content Navigation

● Computer Architecture

As an IC designer, you must be familiar with computer composition and architecture

Principles of computer composition

● Standard bus interface protocol

Including common bus standards and interface protocols. Standard handshake timing refers to FIFO, RAM handshake and cross clock domain handshake widening method

Standard Handshake Timing

Standard Bus Interface Protocol