Digital IC design study notes
Metastable
1. 亚稳态概念
2. 产生原因
3. 解决方法
4. MTBF平均失效时间
1. Metastability concept
Metastable state : Metastability, the trigger cannot reach a confirmable state within a certain period of time. When a flip-flop is in a metastable state, it is impossible to predict the output level of the unit, nor can it predict when the output will stabilize at a certain correct level. During this stable period, the flip-flop outputs some intermediate levels, or may be in an oscillating state, and this useless output level can be cascaded down along the various flip-flops on the signal path.
2. Causes and hazards
Reason :
- Synchronization system: The delay on the combinatorial logic path causes the hold time (Th: hold time) and setup time (Tsu: setup time) of the trigger not to be satisfied;
- Asynchronous reset system: the reset signal will be effective near the clock edge at any time, and the recovery time is not satisfied;
- Cross clock domain: asynchronous signal transmission between two clock domains;
Harm :
- Lead to logical misjudgment;
- Leading to metastable propagation, making different judgments with other cascaded digital devices, making the logic confused;
- The metastable state in the asynchronous reset circuit can cause reset failure and system error;
3. Solution
- Reduce the system clock frequency;
- Use quick-response triggers;
- Asynchronous reset system: asynchronous reset, synchronous release;
- Introduce a synchronization mechanism to prevent metastable propagation; (two beats, asynchronous FIFO)
4. MTBF average failure time :
MTBF : Mean Time Between Failure, mean time to failure. Refers to the average time interval between occurrence of metastable state.
- tr: The longest period of metastable oscillation without causing the synchronizer to fail;
- To, z: related to the electrical characteristics of the trigger;
- fin: asynchronous input signal frequency;
- fclk: the clock frequency of the trigger for synchronization;
It can be known from the formula:
MTBF is related to the process of the device, design specifications and timing margin in the synchronization logic;
MTBF is closely related to the clock frequency of the flip-flop, but the probability of occurrence of metastability has nothing to do with the clock frequency;
Ways to improve MTBF :
- Transistors with more advanced technology: faster supply voltage, faster stability of metastable signals
- Use synchronous chain to improve Tr/z
[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~