Digital IC design study notes _ sequence detection

Digital IC design study notes

6. Sequence detection

1. 设计思想
2. Verilog 代码
3. Modelsim仿真

• Detection sequence "Hello"

1 Design ideas

1. Data stream input waits for "H", if "H" is detected, enter state 2; otherwise, it keeps waiting for "H"
2. Check whether the current character is "e", if it is "e", enter state 3, otherwise return 1;
3. Check whether the current character is "l", if it is, enter state 4; otherwise, return to state 1;
4. Check whether the current character is "l", if it is, enter state 5; otherwise, return to state 1;
5. Check whether the current character is "o", if it is, drive the led control pin, the state is reversed, and return to state 1, waiting for the next "H"; otherwise, return to state 1;

2 Verilog code

module fsm_hello#(//one hot code
	parameter CH_H = 5'b00001,//00001 
	parameter CH_e = 5'b00010,//00010
	parameter CH_l1 = 5'b00100,//00100
	parameter CH_l2 = 5'b01000,//01000
	parameter CH_o = 5'b10000 //10000

)
(
	input clk, //50M
	input rst_n,
	input [7:0] data, //ASCII code
	
	output reg led
);
	reg [4:0] state;

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			led <= 1'b1;
			state <= CH_H;
			end else begin
				case(state)
					CH_H:
						if(data == "H")begin
							state <= CH_e;
							led <= led;
						end else begin
							state <= CH_H;
							led <= led;
							end
					CH_e:
						if(data == "e")begin
							state <= CH_l1;
							led <= led;
						end else begin
							state <= CH_H;
							led <= led;
							end
					CH_l1:
						if(data == "l")begin
							state <= CH_l2;
							led <= led;
						end else begin
							state <= CH_H;
							led <= led;
							end
					CH_l2:
						if(data == "l")begin
							state <= CH_o;
							led <= led;
						end else begin
							state <= CH_H;
							led <= led;
						end	
					CH_o:
						if(data == "o")begin
							state <= CH_H;
							led <= ~led;
						end else begin
							state <= CH_H;	
							led <= led;
							end
						default: begin
							state <= CH_H;
							led <= led;
						end
				endcase
				
			end
	end

endmodule

`timescale 1ns/1ns
`define clock_period 20

module tb_fsm_hello;
	reg clk;
	reg rst_n;
	reg [7:0] ascii;
	wire led;
	
	fsm_hello uut(
		.clk(clk),
		.rst_n(rst_n),
		.data(ascii),
		.led(led)
	);
	
	initial clk = 1;
	always #(`clock_period/2) clk = ~clk;
	
	initial begin
		rst_n = 0;
		ascii = 0;
		#(`clock_period*200);
		rst_n = 1;
		#(`clock_period*200+1);
		forever begin
			ascii = "I";
		#(`clock_period);
			ascii = "A";
		#(`clock_period);
			ascii = "M";
		#(`clock_period);
			ascii = "Y";
		#(`clock_period);
			ascii = "H";
		#(`clock_period);
			ascii = "M";
		#(`clock_period);
			ascii = "n";
		#(`clock_period);
			ascii = "A";
		#(`clock_period);
			ascii = "H";
		#(`clock_period);
			ascii = "e";
		#(`clock_period);
			ascii = "l";
		#(`clock_period);
			ascii = "l";
		#(`clock_period);
			ascii = "o";
		#(`clock_period);
			ascii = "A";
		#(`clock_period);
			ascii = "M";
		#(`clock_period);
			ascii = "X";
		#(`clock_period);
			ascii = "A";
		#(`clock_period);
			ascii = "M";
		#(`clock_period);
			ascii = "X";
		#(`clock_period);		
		
		end
		
		
	end

endmodule

2. Modelsim simulation

[Note]: Personal study notes, if there are mistakes, please feel free to enlighten me, this is polite~~~