Digital IC design study notes
FIFO depth calculation
1. 背景
2. 数据突发长度(burst length)
3. FIFO深度计算
1. Background
We often encounter this scenario in digital IC design. Two modules working in different clock domains need to transfer data between them. In order to avoid data loss, we will use FIFO. When the rate of reading data is lower than the rate of writing data, we have to cache the data that has not been read. Then how much space do we need to cache the data? If the cache is enlarged, resources will be wasted, and if it is small, data will be lost. How to calculate the minimum FIFO depth is the focus of our discussion.
2. Data burst length (burst length)
Before explaining how to calculate the FIFO depth, let's understand a term burst length, if you already know it, you can skip it. To understand the burst length of data, first let us consider a scenario. If module A continuously writes data to the FIFO, module B also continuously reads data from the FIFO. The difference is the clock frequency of module A writing data. It is greater than the clock frequency of module B to read data, so there will always be some data that has not been read away in a period of time. If the system has been working, the data that has not been read away will accumulate more and more, so the depth of the FIFO The need is infinite, so it makes sense to discuss the FIFO depth only during burst data transmission. In other words, we transfer one packet of data at a time and then transfer the next packet of data. We call the number of data transferred within a period of time as burst length. In Wikipedia, burst transmission is explained like this: In telecommunication, a burst transmission or data burst is the broadcast of a relatively high-bandwidth transmission over a short period.
After we know the burst length, through the above discussion, we probably know that the minimum depth of the FIFO is related to the burst rate, burst size, read and write frequency and other factors. To determine the depth of the FIFO, the key is to calculate how many data has not been read during the burst read and write period. That is to say, the minimum depth of the FIFO is equal to the number of data that has not been read.
In fact, in some ASIC forums, many predecessors have given the FIFO depth calculation formula, but when I saw the formula at that time, I didn’t understand how it came. In order to let everyone better understand the calculation process of FIFO size, I don’t apply it here. Calculate the FIFO depth in different scenarios step by step on the premise of the calculation formula. Of course, the calculation formula of the FIFO depth will be given at the end of this article. Comrades who just want to apply the formula can move directly to the end of this article.
Before discussing, we assume that the clock frequency of module A to write data to the FIFO is fa, and the clock frequency of module B to read data from the FIFO is fb.
3. FIFO depth calculation
场景1：fa>fb with no idle cycles in both write and read
Assumption:
Write data clock frequency fa=80MHz
Read data clock frequency fb=50MHz
Burst length = number of data to be transferred = 120
In the burst transfer process, data is continuously read and written
Then:
- The time required to write a data = 1/80MHz = 12.5ns
- In burst transmission, the time required to write all data = 120*12.5ns = 1500ns
- The time required to read a data = 1/50MHz = 20ns
- So it takes 1500ns to write all burst data
- The number of data that can be read in 1500ns = 1500ns/20ns = 75
- So the number of data that has not been read in 1500ns = 120-75 = 45
- So the minimum depth of FIFO is 45
场景2：fa>fb with two clock cycle delay between two successive read and write
Scene 2 adds an assumption on the basis of Scene 1, that is, reading is two beats slower than writing. This assumption really exists. In asynchronous FIFO design, we need to judge whether the FIFO is full or empty to ensure the correctness of the logic. To judge the full or empty flag, we need to compare the read and write pointers, and the read and write pointers are at different locations. In the clock domain, we need to use Gray codes and two-level synchronization registers to reduce the probability of metastable state, and the two-level synchronization will inevitably cause the judgment of the empty or full flag to be delayed by at least 2 cycles. For the empty flag bit, it takes at least 2 clocks to synchronize the write pointer to the read clock domain, and new data may be written during the synchronization period, so the synchronized write pointer must be less than or equal to ( It is equal to the current write pointer only if there is no new data written in the synchronization time, so the judgment at this time is not necessarily a vacuum; similarly, for the full flag bit, synchronize the read pointer to the read clock The domain needs to spend at least 2 clocks, and it is possible that new data will be read during the synchronization period. Therefore, the read pointer after synchronization must be less than or equal to the current read pointer, so the judgment at this time is not necessarily true.
- Through the above discussion, it can be known that the minimum FIFO depth of scene 2 should be slightly larger than the minimum FIFO depth of 45 of scene 1.
场景3：fa > fb with idle cycles in both write and read
Assumption:
Write data clock frequency fa=80MHz
Read data clock frequency fb=50MHz
Burst length = number of data to be transferred = 120
Write once
every 1 cycle Read once every 3 cycles
Then:
Write once every 1 cycle, which means that only 2 cycles will write one data.
Read once every 3 cycles, which means that only 4 cycles will read one data.
- The time required to write a data = 2*1/80MHz = 25ns
- In burst transmission, the time required to write all data = 120*25ns = 3000ns
- The time required to read a piece of data = 4*1/50MHz = 80ns, so it takes 3000ns to write all burst data
- The number of data that can be read within 3000ns = 3000ns/80ns = 37.5
- So the number of data that has not been read within 3000ns = 120-37.5 = 82.5
- So the minimum depth of FIFO is 83
场景4：fa > fb with duty cycles given for wr_enb and rd_enb.
Assumption:
Write data clock frequency fa=80MHz
Read data clock frequency fb=50MHz
Burst length = number of data to be transferred = 120 The
proportion of the write enable signal to the entire burst time is 1/2 The proportion of the
read enable signal to the entire burst time Is 1/4
Then:
- The description of scene 4 and scene 3 are inconsistent, but the situation is the same, so the minimum depth of the FIFO is also 83
场景5：fa < fb with no idle cycles in both write and read
Assumption:
Write data clock frequency fa=40MHz
Read data clock frequency fb=50MHz
Burst length = number of data to be transferred = 120
In the burst transfer process, data is continuously read and written
Then:
- Since reading data is faster than writing data, FIFO only plays a role in the clock domain, and the minimum depth of FIFO is 1
场景6：fa < fb with idle cycles in both write and read
Assumption:
Write data clock frequency fa=40MHz
Read data clock frequency fb=50MHz
Burst length = number of data to be transferred = 120
Write once
every 1 cycle Read once every 3 cycles
Then:
Write once every 1 cycle, which means that only 2 cycles will write one data.
Read once every 3 cycles, which means that only 4 cycles will read one data.
- The time required to write a data = 2*1/40MHz = 50ns
- In burst transmission, the time required to write all data = 120*50ns = 6000ns
- The time required to read a data = 4*1/50MHz = 80ns
- So it takes 6000ns to write all burst data
- The number of data that can be read in 6000ns = 6000ns/80ns = 75
- So the number of data that has not been read in 6000ns = 120-75 = 45
- So the minimum depth of FIFO is 45
场景7：fa = fb with no idle cycles in both write and read
Assumption:
write data clock frequency fa=50MHz
read data clock frequency fb=50MHz
burst length = number of data to be transferred = 120
Then:
- If the read and write clocks are of the same origin and there is no phase difference, then FIFO is not needed; otherwise, the minimum depth of FIFO is 1
场景8：fa = fb with idle cycles in both write and read
Assumption:
Write data clock frequency fa=50MHz
Read data clock frequency fb=50MHz
Burst length = number of data to be transferred = 120
Write once
every 1 cycle Read once every 3 cycles
Then:
Write once every 1 cycle, which means that only 2 cycles will write one data.
Read once every 3 cycles, which means that only 4 cycles will read one data.
- The time required to write a data = 2*1/50MHz = 40ns
- In burst transmission, the time required to write all data = 120*40ns = 4800ns
- The time required to read a data = 4*1/50MHz = 80ns
- So it takes 4800ns to write all burst data
- The number of data that can be read in 4800ns = 4800ns/80ns = 60
- So the number of data that has not been read in 4800ns = 120-60 = 60
- So the minimum depth of FIFO is 60
场景9：Data rates are given，read and write random(important!!!)
In the previous scenarios, the conditions we gave were to read and write once every few clocks. This kind of periodic read and write is very common in practice. However, there is still such a situation in engineering design, where only the read and write rate of data within a period of time is given, and how to read and write is completely random. In this case, we need to consider the worst case to avoid data loss. In the worst case, the difference between the read and write rates should be the largest, which means that the maximum write rate and the minimum read rate need to be found.
Assumption:
Write data clock frequency fa=80MHz
Read data clock frequency fb=50MHz
In the write clock cycle, 40 data are written into the FIFO every 100 cycles
In the read clock cycle, 8 data can be read out every 10 cycles FIFO
So:
First of all, the burst length of the data is not given here. From the assumption, it can be concluded that 40 data are written into the FIFO every 100 cycles. Some people here may say that the burst length is 40 data, but this is not the case. , Because the data is randomly written into the FIFO, we need to consider the bad situation, that is, the situation with the largest write rate. Only the back-to-back situation in the following figure is the situation with the highest write rate, and the burst length is 80
Note: Here you need to verify whether there is a solution , that is, the time to write burst data must be greater than or equal to the time to read burst data, otherwise the data will accumulate more and more, making the FIFO depth must be infinite.
First, the time required to write 80 data = 1/80MHz*(80 100/40)=2500ns, the time required to read 80 data = 1/50MHz (80*10/8)=2000ns, because the burst data is written The time is longer than the time for outburst data, so there is a solution.
Let's calculate the minimum depth of FIFO:
- The fastest time required to write 80 data continuously = 1/80MHz * 80 = 1000ns
- At least the time required to read a data from the FIFO = (1/50MHz) * (10/8) = 25ns
- Then the data that can be read in 1000ns = 1000ns/25ns = 40
- Data not read within 1000ns = 80-40 = 40 So the minimum depth of the FIFO is 40
to sum up
From the above analysis, the minimum depth of FIFO mainly has the following points:
- Before solving, it is necessary to verify whether the amount of data written within the maximum time length allowed is equal to the amount of data read to ensure that there is a solution;
- For the FIFO depth, the worst case needs to be considered. The read and write rates should have the largest difference, that is to say, the maximum write rate and the minimum read rate need to be found;
- Regardless of the scenario, to determine the depth of the FIFO, the key is to calculate how many data has not been read during the burst read and write period;
- Due to the delay in judging the FIFO empty or full flag bit, some margin needs to be reserved in practical applications.
Let's derive the formula for solving the FIFO depth below, assuming:
- The write clock frequency is fwr
- The read clock frequency is frd
- In the write clock cycle, n data are written into the FIFO every m cycles
- In the read clock cycle, there can be y data read FIFOs in every x cycles
Then:
- Must first satisfy (1/fwr) (m/n) ≥ (1/frd) (x/y)
- The "back-to-back" situation is the worst case for FIFO reading and writing. Burst length B = 2*n The fastest time required to write burst length data T = (1/fwr) * B
- It takes at least time t = (1/frd) * (x/y) to read a piece of data from the FIFO
- The number of data that can be taken from both in T time = T/t = B * (frd/fwr) * (y/x)
- The number of data that have not been read in T time = B-B * (frd/fwr) * (y/x)
- Therefore, the minimum depth of the FIFO is B-B * (frd/fwr) * (y/x) (note that some margin is reserved)
—Reprinted content is from Xingyu Yeche Thanks^^
https://www.cnblogs.com/dxs959229640/p/8144656.html
[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~