Table of contents
2. The process of digital IC design and the work required for each process
1.1 Determine project requirements
foreword
- The digital IC design process is the first lesson for IC practitioners.
- Whether you are doing front-end, back-end, or verification, you need to have a basic understanding of the entire design process of the chip.
- You don't need to know more about this content, but you have to know it!
1. Chip design flow chart
Design Flow:
Digital front-end design --> Verification --> Synthesis -->STA -->DFT --> Digital backend --> Post-imitation /Signoff --> Tape-out
2. The process of digital IC design and the work required for each process
Below I use the flow chart to sort out the four major steps of the design and the things to be done, which are mainly divided into four steps:
1.1 Determine project requirements
First of all, there needs to be a market for a chip. Generally, companies will do market research first. For example, artificial intelligence chips, Internet of Things chips, and 5G chips that are relatively popular in the market recently have relatively large demand. With the market demand, we can design the spec of the chip . First, the architecture engineer designs the architecture, determines the functions of the chip, and then uses the algorithm to simulate and simulate, and finally draws a feasible chip design scheme. With the spec of the chip, the next step is to do RTL conding.
1.2 Front-end design
- RTL ( register transfer level) design : Use hardware description languages, such as VHDL, Verilog, System Verilog, to describe the circuit based on the transfer between registers.
- Functional simulation : DV engineers usually complete this part of the work, and verify the circuit function by building a testbench.
- Logic synthesis : Logic synthesis is the process of converting the behavior-level description of the circuit, especially the RTL-level description , into a gate-level expression . That is to translate the code into various actual components.
- STA : (static timing analysis) Static timing analysis, that is, applying a specific timing model to analyze whether a specific circuit violates the timing constraints given by the designer.
The entire IC design process is an iterative process. If each step cannot meet the requirements, the previous process must be repeated until the requirements are met before proceeding to the next step.
In addition to the above steps, another step in front-end design is DFT. As chips become larger and larger, DFT becomes an essential step. DFT (design for test) usually tests defects in the chip production process (such as physical defects, material defects, packaging defects, etc.).
After completing the above work, the nestlist is generated and handed over to the backend.
1.3 Backend design
The following figure shows the process and main work of the back-end design.
Place & Route is generally done by back-end engineers, Physical Design Engineer.
The DRC in the backend is to check whether the design rules meet the requirements of the chip manufacturer, so that the chip can be produced correctly.
Last family portrait:
Here I will not give a specific introduction to each step, because there are too many contents, and each point can be dug in depth.
After the backend completes the work, it will finally generate a file in GDSII format, which will be handed over to the chip manufacturer for tape-out.
