1. Brief description
FPGA is also indispensable for a complete IC EDA environment. FPGA prototype verification is an important part of the IC design process. A chip needs to invest a lot of manpower, financial resources, and a long R&D cycle from design to tapeout. If the tapeout fails, it will be a great loss for the company. At the same time, it is a major loss for the R&D engineers. If the design mistakes are made, the internal will be held accountable, so verification is particularly critical. Many design bugs can be found. FPGA verification is verified on the real circuit, and some bugs not found by the simulator can be found. If the design chip is soc , Then you can also carry out embedded development for the chip function on the FPGA, without waiting for the chip to come back for development, shortening the entire chip development cycle. FPGA prototype verification is a more complicated task. What I am talking about here is more general, and friends who want to know suggest something to search.
But for us, it is an amateur development. It is impossible to go through the complete IC development process from front-end to back-end. However, in order to get a better learning effect, we have to choose: Design=>Front imitation=>FPGA, and DC synthesis may be added later Unlike post-imitation, there is no back-end process, so it is very important to build an FPGA environment. This environment can also be changed to say: develop FPGA under linux.
2. IC project directory structure
At present, it is tentatively determined as the following directory structure, as shown in the figure for a breathing light project, but it will be changed according to the specific situation of the project in the future, please refer to the actual situation;
1) First-level catalog of IC project:
- FPGA: Store FPGA related files
- module: store the project source code
- script: The script that stores the project, which has not been used yet
- tb: store test cases
- verification: Simulation verification directory
2) FPGA project directory:
- constraint: Place FPGA constraint file
- libs: Place FPGA IP core
- script: store FPGA synthesis script
- work: FPGA synthesis directory
3. FPGA environment construction
I am currently using Xilinx's K325T FPGA board. The previous article also said that Vivado 2019.1 has been installed in the EDA environment. The installation under Linux is very simple, so I don’t talk about how to install Vivado here. You need the Vivado installation backstage to reply "vivado". obtain.
1) Add vivado environment
In the home directory, open .bashr, add the following command, modify the path according to your own, and remember to source after saving and exiting to make the environment effective. Then enter "vivado" in the terminal to start the vivado gui.
source /home/Xilinx/Vivado/2019.1/settings64.sh
2) FPGA Tcl script
The following is the Tcl script synthesized by vivado, modified according to your own Xilinx FPGA board.
- My board is a differential clock and uses the IP of clk_wizd;
- The last line generates the mcs file programmed by Flash, which needs to be adjusted according to the Flash model on board;
- According to the number of processors allocated by your virtual machine, set maxThreads. If the script setting exceeds the actual allocation, a comprehensive error will occur. This problem pits me for a day;
#################################################
# vivado FPGA environment configuration
#################################################
set PRJ_NAME Breath_led
set SCRIPT_DIR ../script
set CONST_DIR ../constraint
set DEVICE_NAME xc7k325tffg676-2
set XDC_FILE $CONST_DIR/pin.xdc
set CODE_FILE ../../module/breath_led.v
################################################
#Step1: Create project and overwrite old files
################################################
create_project -force $PRJ_NAME ./ -part $DEVICE_NAME
read_xdc $XDC_FILE
add_file $CODE_FILE
add_files ../libs/sysclk_wiz/sysclk_wiz.xci
set_property ip_repo_paths ../libs/sysclk_wiz [current_project]
set_property verilog_define {
FPGA_SYN=1} [get_filesets sources_1]
#set max threads
set_param general.maxThreads 8
# Launch Synthesis
launch_runs synth_1
wait_on_run synth_1
# Launch Implementation
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
write_cfgmem -format mcs -size 128 -interface BPIx16 -loadbit {
up 0x0 "Breath_led.runs/impl_1/breath_led.bit" } -checksum -force -disablebitswap -file Breath_led.runs/impl_1/Breath_led.mcs
3）Makefile
Need to say "open", this can automatically start vivado gui and automatically load the integrated project.
clean:
rm -rf *.cache *.hw *.sim *.ip_user_files *.runs
rm -f *.jou *.log *.txt *.xpr
built:
vivado -mode batch -source ../script/create_prj.tcl &
open:
vivado -source open_project ./*.xpr &
4. Vivodo cannot recognize the board
Set the USB compatibility of the virtual machine, the default setting is compatible with usb2.0, my computer is usb3.0, modify as follows.
If it is still not recognized, install the cabel driver, enter the driver directory, and perform root installation. Then restart vivado and the board should be recognized.
cd /home/Xilinx/Vivado/2019.1/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers
5. Summary
At this point, the IC EDA environment has been relatively complete, and new content will be added later, which may be mainly based on projects. Currently, the Hummingbird E203 is being studied and will also be shared based on this environment. If you want to get Breath_led, the backend reply " Breath_led " to get download link.
Demonstration effect of the whole process:
Digital IC EDA environment (vcs2018+verdi2018) Demonstration of amateur development environment for digital IC engineers (support linux automated and efficient development of FPGA)
6. The public account and WeChat exchange area
We just created a WeChat exchange group, welcome to join! ! !
