Digital IC design study notes_cross-clock domain synchronization problem 1_single-bit signal cross-clock domain problem

Digital IC design study notes

Cross-clock domain synchronization problem

1 单比特信号跨时钟域问题
	1.1 慢时钟域--> 快时钟域
	1.2 快时钟域-->慢时钟域

1 Single-bit signal cross-clock domain problem

1.1 Slow clock domain -> Fast clock domain

• Method : two shots with a two-level trigger;

• Note :

1. The probability that the first-level register generates a metastable state and can output stably after passing through itself is about 70%~80%, and the probability that the second-level register can stabilize the output is about 99%, and the subsequent improvement is not obvious, so the data comes in After that, you usually choose to take two shots.
2. Although the data can be stabilized to 0 or 1 after two beats, the stable value of 0 and 1 is random, which has no inevitable relationship with the input.
3. Factors that affect the shock time of the metastable state: the production process of the device, temperature, environment, the time when the register collects the stable state in the metastable state, interference, radiation, etc.

• Verilog code

input syn_clk;
input rst_n;
input asyn_sig;

reg syn_reg1;
reg syn_reg2;
	always@(posedge syn_clk or  negedge rst_n)
		if(!rst_n)begin
			syn_reg1 <= 0;
			syn_reg2 <= 0;
		end else
		begin
			syn_reg1 <= asyn_sig;
			syn_reg2 <= syn_reg1;
		end			

1.2 Fast clock domain -> slow clock domain

• Method 1 :

1. Convert the pulse signal into a level signal in the original clock domain (clka)
2. Pass the level signal to the slow clock domain, and do double beat processing in the slow clock domain (clb)
3. Finally, the synchronized signal is restored to a pulse signal (edge ​​detection method)

• Disadvantages : The period of the pulse signal generated in the fast clock domain must be greater than the clock period of the slow clock domain, otherwise the slow clock domain may still not collect the signal.

• Timing diagram

• Verilog code

//----top module---------------------------------
module fast_to_slow
(
	input clka, rsta, clkb,signala,rstb,
	output signalb 
);
	reg sstate,state1, state2, state3；
//----脉冲信号转换沿信号-----------------------
	always@(posedge clka or negedge rsta)begin
		if(!rsta) state <= 0
		else if(signala) state <=~state;
		else state <=0;
	end
//----沿信号打三拍-----------------------------
	always@(posedge clkb or negedge rstb)begin
		If(!rst) begin
			state1 <= 0; 
			state2<=0; 
			state3<=0;
		end
	else begin
		state1<=state;
		state2<=state1;
		state3<=state2; 
	end
//----上升沿，下降沿同时检测-------------------
assign signalb = state2 ^ state3;

endmodule

• Method 2: Handshake signal

After the signal is collected in the slow clock domain, a signal is fed back to the fast clock domain, and the fast clock domain stops transmitting data.

• Verilog code

// Company: 
// Engineer: 	GloriaHuo
// 
// Create Date:    15:26:46 10/20/2020 
// Design Name: 
// Module Name:    shack_hand 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module shack_hand
(
	input clk1,
	input clk2,
	input rst1,
	input rst2,
	input  din,
	
	output  dout
    );
	reg   din_reg;
	reg   din_reg_asyn;
	reg   din_reg_sync1;
	reg   din_reg_sync2;
	reg   d_ask_asyn;
	reg	d_ask;
//----extend din--------------------//
	always@(posedge clk1 or negedge rst1)begin
		if(~rst1)
			din_reg <= 0;
			else if(din==1)
				din_reg <= 1;
			else if(d_ask == 1)
				din_reg <= 0;
	end
	
//----asyn din_reg from clk1 to clk2---//
	always@(posedge clk2 or negedge rst2)begin
		if(~rst2)
			din_reg_asyn <= 0;
			else
			din_reg_asyn <= din_reg;
	end
//----clk2: synchronos process by two DFF-----//
	always@(posedge clk2 or negedge rst2)begin
		if(~rst2)begin
			din_reg_sync1 <= 0;
			din_reg_sync2 <= 0;
		end else
		begin
			din_reg_sync1 <= din_reg_asyn;
			din_reg_sync2 <= din_reg_sync1;
		end
	end
//----clk1: d_ask --------------------//	
	always@(posedge clk1 or negedge rst1)begin
		if(~rst1)begin
			d_ask_asyn <= 0;
			d_ask <= 0;
			end else
			begin
				d_ask_asyn <= din_reg_sync2;
				d_ask <= d_ask_asyn;
			end
	end

//----dout---------------------//	
	assign dout = din_reg_sync1 & ~din_reg_sync2;
endmodule

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—Part of the content comes from Darwin said the official account, Thanks^^

[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~

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