Digital IC verification study notes_1. Verification introduction

Digital IC verification study notes

1. Verification Introduction

1.1 验证介绍
1.2 System verilog介绍
1.3 UVM介绍

1.1 Introduction to Verification

(1). The verification concept is
mainly used to prove that the design function is correct and conforms to the flow of the design function description
(2). The verification platform

1. Stimulus generator: create a test sequence for DUT, first easy and then difficult to stimulate
2. Detector: Observe DUT input and output
3. Comparator: compare the DUT output with the expected data
4. Clock/Reset: Provide clock and reset signals
5. Inspection result report

(3). Verify the work content

1. Whether the design file is correctly implemented according to the function description document
2. Does the hardware designer have a corner case that is missing?
3. Check whether the design can handle the error response (error response)

(4). Verification tasks:
module level, sub-system level, and chip level

(5). Verification goals:
on time, quality and consumption

1. On time: According to the project plan, consider verifying each node (milestone)
2. Quality Guarantee: Before tape out, find all defects as much as possible
3. Performance, low consumption: shorter time, less manpower to complete the work

(6). Verification cycle:

1. Verification plan: designed test function points, mapping coverage, verification environment structure, regression test list
2. Verification environment: excitation generator, detector, comparator
3. Verification code inspection: missed test incentives; inappropriate random constraints; code structure defects to improve coverage
4. Regression test: All test sequences are executed repeatedly. Random tests can be used to check the incentive scenarios covered by the test to improve coverage
5. Verification completeness check before tape-out: regression test report; coverage data; verification process checklist
6. Post-silicon test: Test tape out with testers, confirm the cause of defects, and remedy methods
7. Escape analysis: Summarize errors and causes, and accumulate experience

1.2 Introduction to System Verilog

(1). Background
In 2002, the organization of the Accelera standard led the development, which is an extended hardware description language and verification language of Verilog.
(2). Core features

1. Interface
2. Object-oriented features (class & package)
3. Random constraints (constrained random)
4. Thread control and communication (process control and communication)
5. Direct programming interface
6. Assertion

1.3 Introduction to UVM

(1). Concept
The SV-based verification methodology library is abstracted out to build a general means of verification environment, and uses standard interfaces to make verification environment more conducive to construction and reuse. Wide practicability.
(2). Purpose
Provide some reusable classes to reduce the workload of horizontal reuse and vertical reuse between projects
(3). UVM learning structure:

1. UVM layout (class library), core mechanism
2. Core UVM components and construction methods
3. Communication method between UVM components
4. Composition of UVM test scene
5. Register model application of UVM

(4). Verification platform:

1. SV
2. SV/C++/Verilog
3. C++/Verilog

(5). Verification tool:

1. This modelsim (mentor)
2. NC-sim(cadence)
3. VCS(synopsys)

(6). Verification work:
12. Inject incentives
13. Set responses
3. Make comparisons (actual data & expected data(c++))

(7). Verification script
per/shell/python/makefile (used to set environment variables)
(8). Learning method
UVM library online search manual, DVT SV/UVM integrated development environment (win/linux)

[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~