Digital IC design study notes _ blocking assignment and non-blocking assignment

Digital IC design study notes

5. Blocking and non-blocking assignment

1 Verilog 代码
2 原理图
3 Modelsim仿真

• Block assignment (block): "=", the statements are executed in order, serial execution
• Non-blocking assignment (unblock): "<=", statements are executed in no order, and executed in parallel
• Note: Do not mix blocking assignment and non-blocking assignment in the same always block

1 Verilog code

module block_unblock(
	input 		clk,
	input 		rst_n,
	input 		a,
	input 		b,
	input 		c,
	
	output reg  [1:0] out //out = a+b+c;
	
);
	
	reg [1:0] d; //d = a+ b; out = d+c;
	
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
//			out = 2'd0;
         out <= 2'd0;
		else begin
//----blocked 1--------------
//		   d = a + b;
//			out = d + c;
//----blocked 2--------------
//			out = d + c;
//			d = a + b;
//----unblocked 1------------
//			out <= d + c;
//			d <= a + b;
//----unblocked 2------------
//         d <= a + b;
//			out <= d + c;
//----unblock 3--------------
			out <= a + b + c;
			
		end
endmodule

2. Schematic diagram
(1). Block1 schematic diagram

(2). block 2 schematic diagram

(3). unblock 1 schematic diagram

(4). unblock 2 schematic diagram

(5). unblock 3 schematic diagram (recommended)

3 Modelsim simulation

block 2 simulation results
// out = d + c;
// d = a + b;
first execute out = d + c; the value of d at this time is the value of the previous clock cycle; then execute d = a + b; The value of d at this time will be collected at the next valid edge of the clock; due to one more level of d register, one beat will be delayed and an error will result.

unblock 1, 2 The simulation result of
unblock 3 simulation result (recommended) is also wrong due to the additional level of d register

[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~