Digital Design FPGA Application Study Notes

# Digital design FPGA application study notes

Chapter 1 FPGA Fundamentals and Circuit Design

FPGA foundation and circuit design include two aspects, one is FPGA foundation and the basic principle of 7 series FPGA, and the other is FPGA circuit design. FPG is widely used in military, medical, industrial, communication and other fields. The following are two experimental boards:

FPGA basics and basic principles of 7 series FPGAs

FPGA Overview

FPGA (Field-Programmable Gate Array), namely Field Programmable Gate Array, is the product of further development on the basis of PAL, GAL, CPLD and other programmable devices. It appears as a semi-custom circuit in the field of application specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gate circuits.
The application of FPGA is very extensive. Here we mainly introduce Xilinx Artix-7 series chips:
Xilinx Artix-7 series devices have high performance and low power consumption at 28 nm, and are especially suitable for the size, weight and power consumption of avionics and communication fields. and cost-sensitive market demands. It is the mainstream of the market to provide a large number of IP cores that can be directly used by developers.
The following picture is a screenshot of the development software VIVADO. You can see some IP cores. Users can also design IP cores themselves. The

system designer can connect the logic blocks inside the FPGA through editable connections as needed, just like a breadboard. in a chip.
The logic blocks and connections of a finished FPGA after leaving the factory can be changed according to the designer's design, so the FPGA can complete the required logic functions.
The following figure is an example of Verilog HDL language. Verilog HDL language is a description of the circuit function. Through specific analysis, you can see the specific implementation of the circuit, you can download the circuit to the FPGA, and let the FPGA realize the functions we describe.

FPGA basic logic structure

Field Programmable Gate Array FPGA is a programmable device. Compared with traditional programmable devices such as PAL, GAL, CPLD, etc., FPGA has a different structure. FPGA uses small lookup tables and small RAMs to realize combinational logic. The table is connected to the input of a D flip-flop, and the flip-flop drives other logic circuits or IOs, thus forming a basic logic unit module that can realize combinational logic functions and sequential logic functions. These modules are connected or connected by metal wires. To the IO input and output module, by loading the programming data into the internal static storage unit, the combinational logic can be realized, and then by cooperating with the flip-flop, the sequential logic can be realized. These are programmable, and finally determine the realization of all functions of the FPGA. . The configuration information of the FPGA is stored in the configuration memory, and the FPGA is configured at the moment of power-on and reset.
The following is a Xilinx Artix-7 xc7a35t chip. The package model is ftg256. Under VIVADO, you can see that his package is 16*16 with 256 pins


. After zooming in, you can see the logic unit and the corresponding pin information

for each CLB is composed of two slices. Xilinx FPGA adopts the concept of LCA (Logic Cell Array), which includes a configurable logic module CLB (Configurable Logic Block), an input and output module IOB (Input Output Block) and an internal connection (Interconnect). ) in three parts.

To master the basic logic structure of FPGA, it is necessary to master how LUT is implemented. FPGA implements logic functions through look-up table LUT.

Example 1: Use a LUT to implement the following functions

. Then the truth table as shown in the figure can be constructed.

7 Series FPGA CLB

The FPGA of the Artix-7 series, model xc7a35t, is in the middle of the Artix-7. It contains 5200 SLICEs, including 3600 SLICELs and 1600 SLICEMs. Each SLICE contains four 6-input lookup table LUTs for a total of 20800 lookup tables. Artix-7A35T can allocate 400Kb of distributed RAM, 200Kb of shift register, 41,600 flip-flops.

Logic functions are implemented through look-up table LUTs, 7 series FPGAs, each look-up table LUT has 6 inputs and two independent outputs.
When implementing a 6-input logic function, A1-A6 is the input and O6 is the output. When implementing two logic functions less than or equal to 5 inputs, A1-A5 is the input, O6 is the output, and A6 is pulled high.

In the figure, we can see that each CB consists of two SLICEs.

Each SLICE contains 4 LUTs and 8 storage elements and other combinational logic

. Each SLICE has 8 storage elements, and the 4 on the right can be configured as latches. triggers or triggers, the 4 on the left can only be configured as triggers. The inputs of the four storage elements on the right are selected by multiplexers, and can be output by using the corresponding look-up table, or external input.
The other four are configured as D flip-flops. The input of these 4 D flip-flops can be the output of the lookup table LUT, or it can be an external input.
An additional provision is that when the storage element on the right is configured as a latch, these 4 flip-flops cannot be used by

SLICE in the FPGA 7 series architecture. They are divided into two categories: those that can implement two's complement operations, shift registers, and memory functions. SLICE, become SLICEM. Its function is relatively complex

, and the look-up table can only realize basic logic functions, which is called SLICEL, and the logic structure is relatively simple.

Usually, full-function SLICEM is used in conjunction with simple-function SLICEL, so that the chip can maintain the ability and performance while achieving low performance. power consumption and low cost.

7 Series FPGA IOBs

CLB can realize the function of FPGA, but to transmit data with the outside world, it must have an IO interface IOB (Input Output Block) that is compatible with the external level. The number of IOBs mainly depends on the number of chip pins. Configuration can configure the electrical characteristics of the FPGA pins, and even configure the pull-up and pull-down modes, which can be compatible with most levels.
The 7 series FPGA has multiple IOBANKs (which can be understood as IO groups), each bank has 50 IOBs, and the specific number of banks depends on the size and package of the FPGA.

The XC7K325T has 10 I/O banks, and the xc7a35tftg256-1 has 4 IO banks because it has 256 pins. They are BANK14, BANK15, BANK34 and BANK35, of which only some pins of BANK34 are available.

In the next entry, we can see the specific information of the IOB. The

IO pin can be configured with a variety of input and output standards. When it is configured as a single-ended mode, such as button input, LED driver, etc., it can be set to LVCMOS, LVTTL, HSTL, PCI, SSTL level standard.
When selecting differential input and output mode (2 IO pins differential input or output), it can be set to LVD, Mini_LVDS, RSDS, PPDS, BLVDS, and differential HSTL and SSTL standards.
The 7 series FPGA pins are also divided into high-efficiency pins HP (high-performance) and wide-range HR (high-range) pins
. The T signal is used to control the input and output tri-state DCITERMDISABLE to set the DCI function to be invalid. DIFFI_IN is used to set whether to use differential model. In most 7 series FPGA devices, the last two pins in each bank are single-ended only, the other pins can be configured for single-ended or differential mode.

7 series FPGA and 7a35tftg256-1 features

• 1. Improved efficient 6-input lookup table technology, configurable as distributed memory.
     
• 1. 36 Kb dual-port block memory with built-in FIFO logic is used for on-chip data caching.
     
• 1. Efficient SelectIO technology, supports DDR3 interface, sampling rate up to 1866 Mb/s.
     
• 1. Built-in serial gigabit transceivers (multi-gigabit transceivers), transmit and receive frequencies from 600 Mb/s up to 6.6 Gb/s up to 28.05 Gb/s.
     
• 1. User-configurable analog input interface (XADC), with dual 12-bit 1MSPS analog-to-digital converters with internal temperature and voltage sensors.
     
• 1. With DSP-specific SLICE, with 25 x 18 multipliers, 48-bit carry accumulator.
     
• 1. The clock management block (CMT) combined with the phase-locked loop PLL and the mixed-mode clock manager MMCM has the advantages of high precision and low jitter, and can realize functions such as frequency division and frequency multiplication, and phase shifting.
     
• 1. Integrated PCIE interface module.
     
• 1. Tons of configurable options.
     
• 1. 28 nm high efficiency low power, low core voltage, low cost design.
     Speed ​​grade
     Artix-7 FPGAs are available in -3, -2, -1, -1l, and -2l speed grades, with the -3 grade having the highest performance.
     The Artix-7 FPGA operates primarily on a 1.0V core voltage, and the device xc7a35tftg256-1 has a -1 speed grade. The core voltage VCCINT of the
     voltage 7a35tftg256 has a maximum voltage of 1.1V and usually works at 1.0V.
     
     
• Auxiliary equipment voltage VCCAUX is up to 2.0V, usually 1.8V.
  
• BRAM voltage VCCBRAM voltage maximum 1.1V, usually work at 1.0V.
  
• The I/O port voltage VCCO is up to 3.6V, usually 3.3V.
  
• Designing a board that includes an FPGA requires designing different voltage sources.
  

FPGA circuit design

The circuit board based on Xilinx xc7a35tftg256-1 is used for learning with FPGA, and a laptop can be added to complete the construction of the pocket laboratory. Mastering the basic circuit design of FPGA is necessary for the functional design and implementation of FPGA. For example, when constraining, it needs to correspond to the pin. To light up the LED, you must know and describe the interface relationship in the project.
There are also a large number of experimental development boards to choose from on a certain treasure. You can choose according to your personal preferences. We do not recommend it here to avoid advertising suspicion.

xc7a35tftg256-1 is divided into four BANKs, BANK14, BANK15, BANK35 and BANK34. Different development boards correspond to different pins. There will be corresponding schematic diagrams in the development board supporting materials. You can find the corresponding pins by viewing the schematic diagrams.

Some common resource pin assignments on development boards are listed below:

• LED
  The LED driver circuit is very simple, and the output I/O port of the FPGA has enough driving capability to drive the LED to light up.
  
  
  
• DIP switch
  DIP switch (also called DIP switch, toggle switch) is an address switch used for operation control
  
  
  
• Buttons
  are an indispensable component of the development board. Different buttons have different electrical characteristics. According to the circuit diagram, when the button is in the default state (not pressed), the corresponding pin is grounded through two series 10K ohm resistors to obtain low level input. When the button is pressed, it is connected to the power supply through a 10K resistor, and a high-level input will be obtained at this time.
  
  

• The selection of nixie
  tubes is divided into conjoined nixie tubes and distributed nixie tubes, the difference between common anode and common cathode, and the driving method is also divided into the difference of including 3-8 decoder and without 3-8 decoder. Using a 3-8 decoder can save chip pin resources.
  
  The following is the circuit board seven-segment digital tube drive circuit and pin assignment diagram
  

• VGA driver
  
  
• Serial driver
  
  
• XADC
  
  

• Other interfaces