Digital IC design study notes _ synchronous circuit, asynchronous circuit, synchronous reset, asynchronous reset

Digital IC design study notes

Synchronous circuit, asynchronous circuit, synchronous reset, asynchronous reset

1. 同步电路，异步电路
2. 同步复位，异步复位
	2.1 同步复位与异步复位的对比
	2.2. 同步复位代码与结构
	2.3. 异步复位代码与结构
	2.4. 异步复位同步释放代码与结构

1. Synchronous circuit, asynchronous circuit

• The main difference between a synchronous circuit and an asynchronous circuit is whether the trigger of the circuit is synchronized with the drive clock;
• From the behavioral perspective: Do all circuits process data synchronously under the valid edge of the clock;

	Synchronous circuit	Asynchronous circuit
Number of clocks	only one	Can be multiple
Clock type	Homeomorphism	1. Different sources; 2. Homologous and different phases
Competitive adventure	no	Have
Design coupling	Fully coupled, not conducive to area and power consumption optimization	No coupling, flexible design
Synthesis/Analysis	simple	complex

2. Synchronous reset, asynchronous reset

• 2.1 Comparison of synchronous reset and asynchronous reset

	Synchronous reset	Asynchronous reset
Features	The reset signal is only valid when the clock valid edge comes. (From the combinational logic setting of DFF-D terminal)	Regardless of whether the clock valid edge comes, as long as the reset signal is valid, it is reset. (From the setting of DFF)
Verilog	always@(posedge clk)	always@(posedge clk or negedge rst)
advantage	1. It is good for emulator simulation 2. It can filter out glitches higher than the clock frequency 3. If it is a fully synchronous sequential circuit, it is good for timing analysis.	1. Simple design 2. Save resources (some device libraries have asynchronous DFF) 3. Asynchronous signal identification is convenient, which is conducive to the use of FPGA's global reset port GSR
Disadvantage	1. The effective duration of the reset signal must be longer than the clock cycle, otherwise it will not be recognized and the reset will be completed. 2. Consider the combinational logic delay and reset delay skew. 3. The accumulated data input needs to be inserted into the combinational logic, which consumes logic resources.	1. Asynchronous signals are susceptible to glitches. 2. Metastable is prone to occur (the reset signal is just near the valid edge of the clock signal when the reset signal is released)
to sum up	It is recommended to use asynchronous reset and synchronous release

• 2.2 Synchronous reset code and structure

module dff_syn(
	input clk,
	input rst_n,
	
	input din,
	
	output reg dout
);
	always@(posedge clk)
		if(!rst_n)
			dout <= 1'b0;
		else
			dout <= din;
endmodule

• 2.3 Asynchronous reset code and structure

module dff_asyn(
	input clk,
	input rst_n,
	
	input din,
	
	output reg dout
);

	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			dout <= 1'b0;
		else
			dout <= din;
endmodule

• 2.4 Asynchronous reset and synchronous release code and structure

module asyn_dff_syn(
	input clk,
	input rst_n,
	
	input din,
	
	output wire dout
);
	reg din_reg0;
	reg din_reg1;
	
	always@(posedge clk or negedge rst_n)
		if(!rst_n)begin
			din_reg0 <= 1'b0;
			din_reg1	<= 1'b0;
		end 
		else begin
			din_reg0 <= din;
			din_reg1	<=	din_reg0;
		end
	assign dout = din_reg1;
	
endmodule

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[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~

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