wx Gong Zhonghao: Chuangxiang Diary
Dialogue Send: Music Circuit
Get the complete non-watermark paper report (including circuit diagram) for free
Article directory
1. Design task requirements
1. Course design topic
Design a music performance circuit that can automatically play the written music. It is required to play the music through the speaker on the experimental box, and use the light-emitting diode to display the beat of the music.
(Additional functions: This design adds many additional functions based on the realization of all the functions required by the topic. All functions will be clarified in the "General Overview of Engineering Design", which is hereby declared.)
2. Design analysis
(1) Basic principle of music hardware playing circuit
The sounding principle of the hardware circuit, the frequency range of the sound is about tens to several thousand Hz, if the program can be used to control a certain pin of the FPGA chip to output a rectangular wave of a certain frequency , connected to the speaker can emit the sound of the corresponding frequency. Each note in the music corresponds to a certain frequency. If you want the FPGA to emit different notes, you only need to control the frequency of the corresponding note. Music is all made up of a series of notes, therefore output the frequency corresponding to these notes successively according to the score of music, just can send the tone of each note continuously on loudspeaker. To accurately play a piece of music, it is not enough to just let the loudspeaker be able to play, but also must accurately control the rhythm of the music, that is, the frequency and duration of each note in the music are the two keys to the continuous performance of the music. factor.
(2) Acquisition of Note Frequency
Multiple signals of different frequencies can be obtained by dividing a certain reference frequency. Since the frequency of each note is mostly non-integer, and the frequency division coefficient cannot be a decimal, the frequency division coefficient obtained by the computer must be rounded to an integer. If the reference frequency is too low, the frequency division coefficient is too small, and the rounding error will be large. If the reference frequency is too high, although the relative error of the frequency can be reduced, the frequency division structure will become larger. In fact, these two factors should be considered comprehensively, and an appropriate reference frequency should be selected on the premise of minimizing the error. Select the reference frequency of 1MHz in this design. The digital frequency divider adopts a 12-bit binary counter. For rests in music, as long as the frequency division coefficient is set to 0, that is, the initial value = 4095, the speaker will not sound at this time.
According to the frequency division coefficient, the initial value obtained by the numerical control frequency divider can be calculated. (Words can no longer describe the principle, and the program can explain this problem. For the explanation of the initial value, please see the program given below.) The calculation
formula of the initial value is as follows: Since the designed digital frequency divider uses 12MHZ as the clock source , and a pulse overflow signal with a frequency of 1MHZ is given by a 12-frequency division, and then the 1MHZ overflow signal is counted with a 12-bit binary code with a preset number, and a frequency that changes with the preset number is given. Pulse signal. Since the pulse signal does not have the ability to drive the buzzer, the frequency of this pulse signal is divided by 2 to drive the buzzer to sound, so the relationship between the frequency of the final output signal and the preset number is as follows:
(3) Control of the rhythm of the music
The minimum beat of the general music is 1/4 beat. If the time of 1 beat is set as 1 second, it only needs to output the duration of 1/4 beat of 4Hz (0.25 seconds). For other occupied time For a longer beat (must be an integral multiple of 1/4 beat), you only need to output the note for the corresponding number of times.
The counting clock signal is used as the control signal for outputting the speed of notes. When the clock is fast, the output beat speed is fast, and the playing speed is also fast. When the clock is slow, the output beat speed is slow, and the playing speed is naturally reduced. It is necessary to add a two-frequency program, so the clock signal of the counter should be 2 times of 4Hz, that is, 8Hz.
(4) Generation of music score
This design stores the note data in the music score in the LPM-ROM. If a sound stays in the logic for 4 clock beats, that is, 1 second, the note will be stored in the LPM- All four consecutive addresses in ROM are stored. When a 4Hz clock comes, a note data is output from the LPM-ROM accordingly.
(5) Selection module
The selection module will use a 4-digit control signal to control the selectivity of the music score module data. It is relatively simple to describe in vhdl language and will not be described in detail here.
(6) Decoder and other modules
Decoder and other modules have been done in previous experiments, and the principle is relatively simple and easy to understand, so I will not elaborate here.
3. Overview of engineering design
When a 4Hz clock pulse comes, the music score generator module outputs a note data to the frequency division coefficient module, and the frequency division coefficient module outputs the initial value required for the frequency division coefficient corresponding to the note, and the initial The value is sent to the digital frequency divider module. When the 12MHz clock pulse comes, the numerical control frequency divider will output the corresponding frequency (that is, the frequency corresponding to the note) to the speaker according to the frequency division coefficient, and the speaker can emit the corresponding note. The sound comes. The continuous 8Hz clock pulse sends the note data stored in the score generator to the frequency division coefficient module one by one, and then passes through the numerical control frequency division module, and finally the speaker sends out the note data one by one. The corresponding voice comes. The song also played smoothly. At the same time, the LED digital tube will display the corresponding score along with the music, and the 3-digit LED lights will flash correspondingly with the frequency of high, medium and low. When the melody is played once, the melody generator can automatically start from the beginning to play in a loop. At this time, use the DIP switch to select the music to be played, and the DIP switch will give the selector a selection signal to select the corresponding song. The data translation module plays the corresponding songs. Four pieces of music are selected in this project and coded in the form of Gray code. Only one bit of the DIP switch is changed each time, which is more convenient for selection. (See Download for the rest of the complete details)
2. Overall frame diagram
The project is composed of modules, four of which are ROMs for music score storage modules, as shown in the figure.
1. The function of the frequency divider is to divide the 50MHz clock provided on the chip into 12MHz and 8Hz clocks, which are used by the counter and frequency division driver (NC frequency divider) respectively.
2. The counter completes the counting function, and the 183 base (the longest song chrysanthemum table has 183 characters) adds one to each clock edge.
3. The four music modules record the scores of 4 songs respectively. Read the data in the corresponding address according to the number counted by the counter of the previous module and pass it to the next module.
4. The selector completes the function of selecting songs.
5. The data translation module translates the data of the address in the song rom selected by the selector into the control data required for the frequency division of the frequency driver (numerical control frequency divider), the data of 3 LED lights (high, middle and bass), and the decoder the required data.
6. The frequency division driver is also a numerically controlled frequency divider, which completes the frequency division function and drives the buzzer.
7. The decoder displays the score data on the LED digital tube.
3. Select the device
See download for details
4. Functional modules
1. The frequency divider (div)
divides the 50MHz clock provided on the chip into 12MHz and 8Hz clocks, which are used by the counter and frequency division driver (NC frequency divider) respectively.
(1) Module graphics:
(2) The program is as follows:
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY div IS
PORT(
clk :IN STD_LOGIC;
CLK12MHz,CLK8Hz: OUT std_logic);
END div;
ARCHITECTURE one of div is
begin
nana:process(clk)
variable cnt:integer range 0 to 2;
variable tmp:std_logic;
begin
if(clk'event and clk='1')then
if cnt>=1 then
cnt:=0;
tmp:=not tmp;
else
cnt:=cnt+1;
end if;
end if;
CLK12MHz<=tmp;
end process nana;
nbnb:process(clk)
variable cnt:integer range 0 to 3125000;
variable tmp:std_logic;
begin
if(clk'event and clk='1')then
if cnt>=3124999 then
cnt:=0;
tmp:=not tmp;
else
cnt:=cnt+1;
end if;
end if;
CLK8Hz<=tmp;
end process nbnb;
end one;
(3) Simulation waveform:
(4) Simulation waveform analysis
It can be seen from the waveform that ckl is an input clock signal of 50MHz, ckl12 is an output clock signal of 12MHz, and clk8 is a clock signal of 8Hz. Due to limited paper, all waveforms are not printed out. .
After analysis, the function of this module is completely correct.
2. Counter (notetabs)
(see download for details)
3. Select the module (choice)
(see download for details)
4. Data translation module (tontaba)
Translate the data of the address in the song rom selected by the selector into the control data required for the frequency division of the frequency driver (numerical control frequency divider), the data of 3 LED lights (high, middle and bass), and the data required by the decoder.
(1) Module image:
(2) The program is as follows:
library ieee;
use ieee.std_logic_1164.all;
entity tonetaba is
port(index:in std_logic_vector (4 downto 0);
code:out std_logic_vector(3 downto 0);
high0:out std_logic_vector(2 downto 0);
tone:out std_logic_vector(11 downto 0))
;
end;
architecture one of tonetaba is
begin
search:process(index)
begin
case index is
when"00000"=>tone<="111111111111";code<="0000";high0<="000";--0/4095
when"00001"=>tone<="011100011111";code<="0001";high0<="001";--L1/1823
when"00010"=>tone<="100000001111";code<="0010";high0<="001";--L2/2063
when"00011"=>tone<="100011110010";code<="0011";high0<="001";--L3/2291
when"00100"=>tone<="100101010101";code<="0100";high0<="001";--L4/2390
when"00101"=>tone<="101000010000";code<="0101";high0<="001";--L5/2576
when"00110"=>tone<="101010111000";code<="0110";high0<="001";--L6/2745
when"00111"=>tone<="101101001011";code<="0111";high0<="001";--L7/2891
when"01000"=>tone<="101110001111";code<="0001";high0<="010";--M1/2960
when"01001"=>tone<="110000001001";code<="0010";high0<="010";--M2/3082
when"01010"=>tone<="110001111001";code<="0011";high0<="010";--M3/3193
when"01011"=>tone<="110010101100";code<="0100";high0<="010";--M4/3244
when"01100"=>tone<="110100001001";code<="0101";high0<="010";--M5/3337
when"01101"=>tone<="110101011100";code<="0110";high0<="010";--M6/3420
when"01110"=>tone<="110110100101";code<="0111";high0<="010";--M7/3494
when"01111"=>tone<="110111000111";code<="0001";high0<="100";--H1/3528
when"10000"=>tone<="111000000101";code<="0010";high0<="100";--H2/3589
when"10001"=>tone<="111000111100";code<="0011";high0<="100";--H3/3645
when"10010"=>tone<="111001010110";code<="0100";high0<="100";--H4/3670
when"10011"=>tone<="111010000100";code<="0101";high0<="100";--H5/3717
when"10100"=>tone<="111010101101";code<="0110";high0<="100";--H6/3758
when"10101"=>tone<="111011010010";code<="0111";high0<="100";--H7/3795
when others=>null;
end case;
end process;
end;
(3) Simulation waveform:
(4) Simulation waveform analysis
由波形可看出，当输入信号index为00110时high0显示1，code显示6（即 中音6），预置初值为101010111000，查询上文所列的表，可发现功能完全正确。
第二个波形图，输入信号00010，输出为中音2，再查预置初值，同样可发现完全正确。因此该模块功能完全正确。
5. Decoder module (deled)
(see download for details)
6. Digital frequency divider module (speakera)
(see download for details)
7. Music score data ROM (four modules)
(see download for details)
8. Selection of address lines:
In addition to the modules mentioned above, the selection of address lines also needs to be added. Different functions of the experimental bottom box have been selected. This experiment uses LED digital tubes, so the assignment of address line vga is vga0 =0, vga1=1, vga2=0, vga3=0. As shown below:
9. The solution of the position selection function of the led digital tube:
this project only needs to display one digit, so a digital tube can be selected. Since the digital tube on the experiment box is a common anode digital tube, it is only necessary to select a digital tube The tube can be assigned to a low level, as shown in the figure: (I have selected 2, 4, 6, and 8 four digital tubes to display together)
5. Overall Design Circuit Diagram
1. Circuit schematic diagram of the top-level design
2. The simulation results of the top-level design
Since the overall input clock signal of the project is 50MHz, which has to pass through multiple frequency dividers and the frequency division coefficient is huge, it is impossible to succeed in the overall simulation (it will cause the simulation time to be too long and fail). Regarding this issue, I specifically asked Mr. Li Bing. The teacher told me to remove a few modules during the simulation and only simulate a part of the functions. The removed modules can be simulated separately to prove the correctness of the entire project. I have thought about this plan for a long time. It is found that this simulation can remove the div frequency division module first, and then change the speakera program (like the simulation of the speakera module) for simulation, or remove the div and speakera modules at the same time for simulation. However, these two methods are also divided into several pieces for simulation, but there is no simulation of the entire project, so this simulation is essentially the same as separately simulating each module to verify the correctness of its function.
As long as the function of each module is proved to be completely correct, it can be concluded that the overall function of the project can be realized. The function of each module has been proved to be completely correct above, so the function of the whole project is also completely correct. After analysis, the top-level design simulation function is completely correct.
3. The pin assignment diagram of the top-level file of the circuit is as follows
4. Connecting and downloading
This program is implemented on the hardware circuit. CLK is connected to the 50MHz crystal oscillator input; the music selection indicators are respectively connected to IO9, I010, IO11, IO12, and then connected to the LED lights; Then connect to the LED, connect SPKOUT to IO13, and then connect to the speaker.
6. Conclusion
Music performance is widely used in automatic answering devices, mobile phone ringtones, group phones, and intelligent instrumentation equipment. There are many implementation methods, among which, pure hardware is used to complete the music performance. With the improvement of FPGA integration, the price drops, the EDA design tools are updated, and the functions are becoming more and more popular, making the application of this scheme more and more popular. more. Today's digital logic designers are under pressure to design tens of thousands of gates with ever-shorter time-to-market, while designers are not allowed to sacrifice silicon efficiency in order to maintain structural uniqueness. It is not a simple matter to use today's EDA software tools to deal with these problems. FPGA is pre-installed with many constructed parameterized library unit LPM devices. By introducing EDA[1] software tools that support LPM, designers can design products that are structurally independent and use silicon chips very efficiently.
The design and implementation of this FPGA-based music hardware performance circuit not only adopts the VHDL hierarchical and modular design method, but also adopts the design idea of numerical control frequency division and custom LPM-ROM, which better optimizes the design of the music performance digital circuit On this basis, the music can be changed at will without changing the top-level file structure, which effectively shortens the product development cycle, reduces the number of designed chips, reduces power consumption, and improves design flexibility, reliability and scalability.