[Oscilloscope] Design and implementation of digital oscilloscope based on FPGA

1. Software version

quartusii

2. Theoretical knowledge of this algorithm

Block diagram structure:

1. The cache contains trigger control and trigger memory;

2. The sampling rate of 1GsPs is required by the design index, and the final data stream should be reduced to 250MbPs;

3. From the point of view of the indicators, the time from the waveform data acquisition to the final display time should be 10s;

4. The selection of LED should be able to correspond to the waveform mapping module;

5. The entire design mainly consists of two parts, the waveform coprocessor of the FPGA and the final LED display;

6. Two-dimensional display effect, not three-dimensional;

Step 1: Data Acquisition Module 

First, the externally input 1G data is cached through the idea FIFO, and becomes 250M data per channel, that is, one channel of high-speed data is converted into multi-channel low-speed data, so that it can work in the FPGA. At this time, the system clock needs to be multiplied to 250M.

   Then, here the following structure is designed in QII:

Step 2: Oscilloscope Display Module 

       The waveform mapping module is to map the waveform data after sampling to the waveform mapping library. Each storage unit in the mapping library corresponds to a point on the LCD display, so the waveform data of the point to be displayed is converted into amplitude. The amplitude is marked as a value in the vertical direction on the LCD, so each display point after the snapping point corresponds to a pixel point on the LCD. The abscissa represents timing information, and the ordinate represents amplitude information. In this way, the waveform data obtained by multiple sampling can be mapped to the same mapping library, which is equivalent to overlapping and displaying the waveforms collected multiple times, which reflects the effect of high capture rate, and the display effect also achieves high refresh rate. Require.

3. Part of the core code

module display(
					clk,
					cs,
					datain,
					RDADDR,
					x_out,
					y_out,
					da_wrx,
					da_wry
					);
input clk;
input cs;
input [7:0] datain;
output reg [9:0] RDADDR;
output [7:0] x_out;
output [7:0] y_out;
output reg da_wrx,da_wry;

reg link_xout,link_yout;
reg [12:0] counttemp;
reg [2:0] bittemp;
reg [7:0] xbuf;
reg [7:0] ybuf;

parameter 	GET			=	10'b0_000_000_001,
			COMPARE1	=	10'b0_000_000_010,
			COMPARE2	=	10'b0_000_000_100,	
			COMPARE3	=	10'b0_000_001_000,	
			COMPARE4	=	10'b0_000_010_000,	
			COMPARE5	=	10'b0_000_100_000,
			COMPARE6	=	10'b0_001_000_000,
			COMPARE7	=	10'b0_010_000_000,
			COMPARE8	=	10'b0_100_000_000,
			NEWCOUNT	=	10'b1_000_000_000;

reg [9:0] state;

assign x_out=link_xout?xbuf:8'bz;
assign y_out=link_yout?ybuf:8'bz;

always @(posedge clk)
begin
if (cs)
	begin
	state<=GET;
	link_xout<=0;
	link_yout<=0;
	counttemp<=0;
	bittemp<=0;
	da_wrx<=1;
	da_wry<=1;
	end
else
	begin
	link_xout<=1;
	link_yout<=1;	
	case (state)
	default:	begin							//GET
				RDADDR<=counttemp[12:3];
				bittemp<=7-counttemp[2:0];
				state<=COMPARE1;
				da_wrx<=1;
				da_wry<=1;
				end
	COMPARE1:	begin
				da_wrx<=0;
				da_wry<=0;
				if (datain[bittemp])
					begin
					xbuf<={counttemp[6:0],1'b0};
					ybuf<={counttemp[12:7],1'b0};
					state<=COMPARE2;
					end
				else
					begin
					xbuf<=0;
					ybuf<=0;
					state<=NEWCOUNT;
					end
				end	
	COMPARE2:	begin
				da_wrx<=1;
				da_wry<=1;				
				state<=COMPARE3;
				end

	COMPARE3:	begin
				state<=COMPARE4;
				end

	COMPARE4:	begin
				state<=COMPARE5;
				end
									
	COMPARE5:	begin
				state<=NEWCOUNT;
				end							
	NEWCOUNT:	begin
				state<=GET;
				if (counttemp==8191) 
					counttemp<=0;
				else 	
					counttemp<=counttemp+13'b1;								
				end			
	endcase
	end
end

endmodule						

4. Operation steps and simulation conclusion

    The simulation results of the system are as follows:

The meaning of the simulation waveform is:

They are the system clock and the 250M clock, which are used to read the AD data input from the outside.

Rst is the reset signal of the system, and the system works normally when it is 0.

The following four are the signals collected by the idea entering the FPGA. These four signals will pass through the four FIFOs.

Four are the output data of the FIFO, and the last one is the data before being sent to the dual-port RAM, and the idea data is combined into one data.

Address signal to write to RAM.

They are the read address signals stored by the oscilloscope waveform, respectively. x and y are the coordinate positions stored in the external storage area. By reading the positions of different coordinate points, the effect of displaying the waveform is achieved.

5. References

[1] Chu Hua, Wan Qiang, Cao Haiyuan, et al. Design of digital oscilloscope based on DSP and FPGA [J]. Automation Instrumentation, 2013, 34(3):4.A35-12