[Signal generator] Design of a signal generator based on quartusii

1. Software version

Quartusii 12.1

2. The main content of this system

The simulation is simulated by Quartus II 12.0 software, the language is verlog hdl, and it generates rectangular waves, pulse waves, sine waves, and 4-level m-sequence (only one m-sequence is output). After the program is downloaded to the development board, the oscilloscope must be able to observe the waveform. The development board is emp240. It is best to select the waveform you want to output through the buttons on the development board, and you can output it separately if you cannot.

3. Core code

module tops(
            i_clk,//clock
            i_rst,//rest,
            i_key,//key
            o_signal//4 kind of signal
           );
           
input      i_clk;
input      i_rst;
input[1:0] i_key;
output[7:0]o_signal;

wire     signal_cube;
wire     signal_pluse;
wire     signal_m;
wire[7:0]signal_sin;

//the module of juxin signal
signal_jux signal_jux_u(
                  .i_clk    (i_clk),
                  .i_rst    (i_rst),
                  .o_signal (signal_cube)
                 );

//the module of pluse signal
signal_p signal_p_u(
                  .i_clk    (i_clk),
                  .i_rst    (i_rst),
                  .o_signal (signal_pluse)
                 );
           
//the module of m signal
signal_mseq signal_mseq_u(
                  .i_clk    (i_clk),
                  .i_rst    (i_rst),
                  .o_signal (signal_m)
                 ); 
 
 
//the module of sin signal          
signal_sin2 signal_sin2_u(
                  .i_clk    (i_clk),
                  .i_rst    (i_rst),
                  .o_signal (signal_sin)
                 );       
      
 
reg[7:0]o_signal; 
always @(posedge i_clk or posedge i_rst)
begin
     if(i_rst)
     begin
     o_signal <= 8'd0;
     end
else begin
     case(i_key)
     0:o_signal <= {signal_cube,7'b000_0000};
     1:o_signal <= {signal_pluse,7'b000_0000};
     2:o_signal <= {signal_m,7'b000_0000};
     3:o_signal <= signal_sin;
     default:o_signal <= {signal_cube,7'b000_0000};
     endcase
     end        
end   
   
           
endmodule

4. Operation steps and simulation conclusion

The simulation is simulated by Quartus II 9.0 software, the language is verlog hdl, and it generates rectangular waves, pulse waves, sine waves, and 4-level m-sequence (only one m-sequence is output). After the program is downloaded to the development board, the oscilloscope must be able to observe the waveform.

My cpld development board is emp240. It is best to select the waveform you want to output through the buttons on the development board, and you can output it separately if you cannot.