FPGA clock domain crossing treatment

FPGA clock is the heart of the whole system, if the abnormal heartbeat each module, cause inconsistent hands and feet.

Cross-clock processing There are three ways :

1. Control signal pulse detection method suitable for fast clock cycle and slow clock;
2. Handshake method for mining a fast clock slow clock;
3. Asynchronous fifo method is suitable for mass data transmission

Pulse Detection       

The rising edge of the fast clock, using two or three registers, the detection enable signal slow clock domain, and generates a pulse signal in a period of the fast clock domain.

input    clk；
input    rst；
input    wr_en；

reg      wr_r；
reg      wr_r2；
wire     pos_wr;

always@(posedge clk ,negedge rst)
begin
    if(rst)begin
        wr_r <= 1'b0;
        wr_r2<= 1'b0;
    end else 
        wr_r <= wr_en;
        wr_r2 <= wr_r;
    end
end

assign    pos_wr= !wr_r && wr_r2 ; //写选通信号上升沿，拉高一个周期的脉冲信号

Handshake method

Fast clock domain generates write requests and data, that the slow clock domain detected a write request, generating the response data latch signal, after detecting the fast clock domain response signal, a write request is withdrawn, thereby completing a write operation.

module handshack （
    input        clk,
    input        rst_n,
    input        req,
    input  [7:0] datain,
    output       ack,
    output       data_out
）
//****************************
//上升沿信号检测
reg    req_r ,req_r2,req_r3 ;
always@ (posedge clk or negedge rst_n)
begin
    if (!rst_n)begin
        req_r  <= 1'b1 ;
        req_r2 <= 1'b1 ;
        req_r3 <= 1'b1 ; 
    end else begin
        req_r <= req ;
        req_r2 <= req_r ;
        req_r3 <= req_r2 ;
    end
end
        
//pos_req2 比 pos_req1 延时一个时钟周期，确保数据被稳定锁存
wire     pos_req1 =  req_r &&  ~ req_r2 ;
wire     pos_req2 =  req_r2 && ~ req_r3 ; 
//***************************************
// 数据锁存
reg  [7:0]     dataoutr;

always@(posedge clk or negedge rst_n )begin
    if(!rst_n)
        dataoutr <= 8'h0;
    else if(pos_req1)
        dataoutr <= datain ; //检测到req有效后锁存输入数据
end

assign dataout =dataoutr
//**************************************
//产生应答信号ack
reg ackr;

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        ackr <= 1'b0;
    else if (pos_req2)
        ackr <= 1'b1;
    else if(!req)
        ackr <= 1'b0 ;
end

assign ack =ackr;

endmoudle

Asynchronous fifo law

Each read clock according to the clock two clock domains, the control Wreq, and read and write commands req operation.