In FPGA design, the setting of timing constraints is critical to circuit performance and reliability. In the previous article, the basics of FPGA timing constraints have been introduced in detail.
This article will focus on the main clock constraint setting, give detailed constraint commands, and introduce how to write the main clock constraint in Vivado.
1. Master clock constraints
The master clock is the most basic clock in the FPGA circuit, and its stability and accuracy play a vital role in the stable operation of the circuit. In timing constraints, we need to accurately define the clock constraints of the main clock to ensure that the timing constraints of the circuit are achieved.
In Vivado, we can use the create_clock command to define the clock constraints of the main clock, the syntax is as follows:
create_clock -name <clock_name> -period <clk_period> [ -waveform {<rise_time> <fall_time>} ] [get_ports <input_port>]
| parameter |
meaning |
|---|---|
| -name |
used to name the clock |
| -period |
Used to define the clock cycle |
| -waveform |
Waveform parameters can be understood as duty cycle. Within one cycle, rise_time indicates the first rising edge moment, and fall_time indicates the first falling edge moment. |
| get_ports |
Specify the module clock signal name in the project |
It should be noted here that the clock created using create_clock must be the primary clock.
There are usually two sources of master clocks in FPGAs:
-
Provided by an external clock source (crystal oscillator), entered through a pin.
-
For FPGA chip models with high-speed transceiver (GT), there is GT clock RXOUTCLK or TXOUTCLK.
For Xilinx 7 series FPGAs, you need to add constraints to both GT clocks, but for UltraScale and above series FPGAs, you only need to constrain GT input clocks.
1. Externally input single-ended master clock signal
Set the external clock input from the pin clk, the clock period is 12ns, the duty cycle is 50%, and the phase shift is 0, then the main clock constraints are as follows:
create_clock -period 12 [get_ports clk]
If there is a phase shift of 90, the master clock constraint becomes
create_clock -period 12 -waveform {3 9} [get_ports clk]
2. External input differential clock signal
The PGA differential clock refers to the clock signal coming in through the P terminal and the N terminal of the clock pin. It is usually used in occasions with high frequency or high precision requirements, and its function is to eliminate common mode noise, thereby improving system performance.
Only the P terminal of the differential clock needs to be constrained, and the P terminal and the N terminal cannot be constrained at the same time, and the N terminal can be automatically recognized by the software.
For example, the differential clock sys_clk_p and sys_clk_n, the clock cycle is 6.667ns, then the constraint is:
create_clock -name sys_clk -period 6.667 [get_ports sys_clk_p]
3. High-speed transceiver GT clock signal
The FPGA high-speed transceiver GT clock signal means that when the high-speed transceiver GT (Gigabit Transceiver) is used for signal transmission and reception in the FPGA, a clock signal matching its rate needs to be used for synchronous transmission. Doing so can ensure stable signal transmission and avoid possible bit errors in data transmission.
For example, the clock source is provided by the high-speed transceiver gt0, the timing constraint is:
create_clock -name rx0_outclk -period 3.333 [get_pins gt0/RXOUTCLK]
create_clock -name tx0_outclk -period 3.333 [get_pins gt0/TXOUTCLK]
Second, Vivado adds timing constraints
1. Create a new XDC file, or add an existing XDC file
Click the "+" sign, select "add or create constras", and click Next.
Select "create file" and fill in the timing file name.
2. Add timing constraints
(1) Method 1
Open the XDC file directly and write the timing constraint statement
(2) Method 2
After the project synthesis is completed, click "Open Synthesized Design", wait for the opening to complete, directly enter the timing constraint statement in the TCL console window, and press Enter.
(3) Method 3
After the project synthesis is completed, click "Edit Timing Constraints" and wait for the GUI interface to open.
Select the constraint type to be created in the "Classification Area", click the "+" sign to create a constraint, and the constraint creation interface will pop up.
Click "..." on the right side of source objects to open the module interface search interface, and click the find button, select the "sys_clk" signal, click the "right arrow", and finally click set.
Finally, enter the clock name, clock period, and waveform parameters, click ok, and "ctrl + S" to save.
3. Summary
The main clock constraint is a common operation in FPGA and must be mastered. This article has introduced the operation commands and operation demonstration in detail, hoping to help everyone learn and master this knowledge.
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