Regarding the most commonly used cross-clock domain processing methods, predecessors have summarized a lot, such as dual register processing, fifo, handshake protocol, etc., which are almost perfect and will not be repeated here.
In addition, there is xilinx official timing design guidance document UG906, readers can read and analyze by themselves. Here, an example is given to introduce my way of cross-time domain processing.
This example is an example of hdmi display test. Send the manually generated color bar pixel data through hdmi, and connect it to the hdmi interface of the monitor for display test.
The core part of the design is the encoding module and the serial sending module. dout[9:0] is the encoded data driven by the pixelclk clock, which is sampled and received by the serial transmit module at a clock ( clkx5 ) that is 5 times faster than the pixelclk speed . This involves the cross-clock domain problem of two clocks.
Double-register processing is carried out at the data receiving end, which can solve the metastable problem of sampling and ensure accurate data reception.
However, just doing this is not enough. After the general routing, the timing report shows several timing violations.
The timing shows that the setup time of some paths does not meet:
The specific analysis is that when cross-clock sampling, the settling time is not satisfied, that is, for the high-speed clock, the data from the low-speed clock is too slow to stabilize. In this way, there are two processing ideas, reducing the delay on the data path and delaying the arrival of high-speed clocks.
Based on these ideas, the processing of reducing/increasing the delay is performed on the two clocks respectively.
Look at the wiring diagram of the design:
It can be seen that the two clocks from the PLL are connected to the global clock buffer.
In this way, as long as we change the routing of clk so that it is directly connected to the closer BUFR area buffer, the delay from clock to logic can be reduced.
Add some delay to the clkx5 clock and connect it to the BUFH buffer. After these operations, the result of timing convergence can be achieved.
After processing, the distance between the clk clock and the logic area is closer, reducing the delay.
Finally, the timing closure issue is resolved.
This is an idea of timing processing, I hope it can help everyone!