Reference Documents
https://blog.csdn.net/u011412586/article/details/10009761
Foreword
For signal processing needs across clock domains, the most important thing is to ensure that data can be transferred to a stable sampling clock domains.
Cdc common treatment methods need to focus on similarities and differences between clock domains rate, that is divided slow to fast clock domain clock domain, fast clock domain to a slow clock domain problem, phase relations, will make people instantly explode.
So, if there is a relatively stable, and without concern for data transfer clock domain transfer mode and receive clock domains both clock speed, the phase relationship of it?
Here handshake rope simulation method they want, and do not know with rope method is not consistent. . . . . .
Thinking is: to ensure absolute data is received, the natural response is a handshake mechanism.
Process
Consider first metastable Description: For asynchronous signals acquired, there will inevitably metastable, metastable recovery time but typically one clock or two clocks, which likewise is not an intermediate value of 0 but a developer can not determine the value, the higher your clock frequency at the same time, the probability of occurrence of metastable greater.
Online's feeling uninformed say, for a simple to use multi-level trigger, then use the highest 2bit the edge detection, visual inspection is not enough.
It may be understood as the value of x in the simulation, but the nature of digital circuits is the value, either 0 or 1.
Therefore, if a detection signal is rising, even taken to a metastable state, then two cases:
(1) relatively steep edge, the clock only once taken to the metastable state, the value of the edge may register: 00, 01. 00 is detected, the next time will be taken to 01. If it is detected 01, is wanted along.
(2) that is not steep edge, leading to a clock taken twice or even more times sub-problem, and that this was no play. Because you do not know the current is 00 \ 01 \ 10 \ 11, which may cause you to follow a logical finished.
Of course, the second case will not be considered here, it is not such a bad internal FPGA rising edge may occur, unless your clock too quickly, before the clock edge arrival, the metastable state has not recovered.
Extreme approach is (essentially a filter): register with more bits, for example 8bit, when it is detected as 8'b0000_1111, that is, the rising edge of the matter, although it is absolutely reliable in a wide edge is detected but detected along the longer used, and the need to ensure a high length before low level signal, the filtered otherwise. . . . . .
Therefore, the edge steepness of the signal is very important, jargon is called: the rise time, fall time.
Closer to home, then shook hands rope method is Zeyang does it work?
As shown below: somewhat complex
Shown, the operational flow of FIG: above process should be to support multi-bit data across clock domains, where said multi-bit internal data of the FPGA, pulse_clk1 denotes a transmission data enable, CLK1 is pulled detect enable pulse_delay_clk1 start rope. In clk2, the detected rising edge of clk1 rope signal is generated pulse_clk2, clk2 detected in pulse_clk2 rope pulse_delay_clk2 clk2 is initiated, the rope is detected in the clk1 signal clk2 is high in the solution out of clk1 tie knots. Detecting the low clk1 clk2 hove junction, the solution rope rope in pulse_delay_clk2 clk2 signal, to complete the transfer.
Data to be transmitted is sampled at the rising edge of clk2 rope.
The busy signal is a signal clk1, the transmission data is enabled in the arrival of clk1 is pulled, the falling edge pulse_delay_clk2 is low.
Can be seen, this is only suitable for small amounts of data transfer slow.
Source
`timescale 1ns/1ps module cdc_test ( input i_clk1 , input i_clk2 , // input i_rst_n , input i_en_clk1 , input [15:0] i_data_clk1 , output o_busy_clk1 , output o_valid_clk2 , output [15:0] o_data_clk2 ); ////clk1 ///transmission / clk1 edge detection enabled REG [ . 1 : 0 ] = r_en_clk1_edge 2 ' B00; Always @ ( posedge i_clk1) the begin r_en_clk1_edge <r_en_clk1_edge = {[ 0 ], i_en_clk1}; End REG r_en_clk2 = . 1 ' B0; /// / clk2 edge detection enable REG [ . 1 : 0 ] = r_en_clk2_edge 2 ' B00; Always @ ( posedge i_clk1) the begin r_en_clk2_edge <r_en_clk2_edge = {[ 0 ], r_en_clk2}; End REG r_en_expand = . 1 ' B0; //// clk1 can cause prolonged Always @ ( posedge i_clk1) the begin IF (r_en_clk1_edge == 2 ' B01) r_en_expand <= . 1 ' B1; the else IF (r_en_clk2_edge == 2 ' B01) r_en_expand <= . 1 ' B0; End REG r_busy_clk1 = . 1 ' B0; //// indicate a busy transmission, clk1 busy time data is not changed Always @ ( posedge i_clk1) the begin IF (== r_en_clk1_edge2 ' B01) r_busy_clk1 <= . 1 ' B1; the else IF (r_en_clk2_edge == 2 ' B10) r_busy_clk1 <= . 1 ' B0; End /// / CLK2 REG [ . 1 : 0 ] = r_en_expand_edge 2 ' B00; //// so that the extended can clk1 edge detection Always @ ( posedge i_clk2) the begin r_en_expand_edge <r_en_expand_edge = {[ 0 ], r_en_expand}; End Always @ ( posedge i_clk2) //// clk2 an enable the begin IF (r_en_expand_edge == 2 ' B01) r_en_clk2 <= . 1 ' B1; the else IF (r_en_expand_edge == 2 ' B10) r_en_clk2 <= . 1 ' B0; End REG r_valid_clk2 = . 1 ' B0; Always @ ( posedge i_clk2) the begin IF (r_en_expand_edge == 2 ' B01) //// rising edge of the data is valid r_valid_clk2 <= . 1 ' B1; the else r_valid_clk2<= 1'b0; end reg [15:0] r_data_clk2 = 16'd0; always @(posedge i_clk2) begin if (r_en_expand_edge == 2'b01) ////上升沿刷新数据 r_data_clk2 <= i_data_clk1; end ////信号输出 assign o_busy_clk1 = r_busy_clk1; assign o_valid_clk2 = r_valid_clk2; assign o_data_clk2 = r_data_clk2; endmodule // end the cdc_test model
Simulation and see.
You can see the correct transmission of data, whether it is fast to slow or slow to fast.
Board-level testing it later.
the above.