Introduce the principle of
1, divide
FPGA design clock divider is an important basic knowledge for the division usually use counter to achieve the desired clock frequency, the greater the frequency of the cycle can be seen after the division. Generally to achieve an even number of coefficients in the frequency division programming easier, and the odd division is relatively complex, the fractional harder.
1 ) Dual frequency coefficient = clock input frequency / clock output frequency = 50MHz / 10 = 5MHz , the counter input or falling edge of the clock from 0 to ( 10-1 ) counts the clock and outputs the count to 4 and 9 flip time.
2 ) the odd division factor = 50MHz / 10MHz =. 5 , the two counters are at the rising and falling edges of the clock input from 0 to ( 5-1 ) count, and the corresponding rising and falling edge of the output clock to count 1 and . 4 is reversed, the last two clock outputs oR operation to obtain a duty ratio of 50% of the 5 divided output clock.
The following figure shows the 50MHz input clock 10 and divide- 5 division simulation waveform frequency
2, octave
Two ideas: the PLL (Phase Locked Loop) or use to build gate delay
Note: This simulation is the use of FPGA internal circuit delay multiplier realized the need to see the waveform in the simulation, the output waveform can not be obtained in behavioral simulation.
A clock IP division frequency related parameter description
Input Clock: the Clk_in1 (125MHz)
Output Clock: CLK_OUT1 (50MHz) , CLK_OUT2 (74.25 MHz)
则VCO Freq=1262.5MHz=clk_in1*CLKFBOUT_MULT_F/DIVCLK_DIVIDE=125*50.5/5
clk_out1(50MHz)=VCO_Freq/Divide=1265.5/25.250
clk_out2(74.25MHz)=VCO_Freq/Divide=1265.5/17
Two, MMCME4_ADV
MMCME4 is a mixed signal block, for supporting frequency synthesis, clock network design and reduce jitter. Based on the same VCO frequency can have a separate output clock frequency, duty cycle, and phase shift. In addition, MMCME4 also supports dynamic phase shift and fractional divider
( 1 ) Verilog initialization template
MMCME4_ADV #(
.BANDWIDTH("OPTIMIZED"), // Jitter programming
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB
.CLKFBOUT_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKIN2_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0
.CLKOUT0_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT1_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT1_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT2_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT2_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT3_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT3_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT4_CASCADE("FALSE"), // Divide amount for CLKOUT (1-128)
.CLKOUT4_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT4_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT4_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT5_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT5_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT5_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT6_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT6_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT6_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT6_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.COMPENSATION("AUTO"), // Clock input compensation
.DIVCLK_DIVIDE(1), // Master division value
.IS_CLKFBIN_INVERTED(1'b0), // Optional inversion for CLKFBIN
.IS_CLKIN1_INVERTED(1'b0), // Optional inversion for CLKIN1
.IS_CLKIN2_INVERTED(1'b0), // Optional inversion for CLKIN2
.IS_CLKINSEL_INVERTED(1'b0), // Optional inversion for CLKINSEL
.IS_PSEN_INVERTED(1'b0), // Optional inversion for PSEN
.IS_PSINCDEC_INVERTED(1'b0), // Optional inversion for PSINCDEC
.IS_PWRDWN_INVERTED(1'b0), // Optional inversion for PWRDWN
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
.REF_JITTER2(0.0), // Reference input jitter in UI (0.000-0.999).
.SS_EN("FALSE"), // Enables spread spectrum
.SS_MODE("CENTER_HIGH"), // Spread spectrum frequency deviation and the spread type
.SS_MOD_PERIOD(10000), // Spread spectrum modulation period (ns)
.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked
)
MMCME4_ADV_inst (
.CDDCDONE(CDDCDONE), // 1-bit output: Clock dynamic divide done
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit output: Feedback clock stopped
.CLKINSTOPPED(CLKINSTOPPED), // 1-bit output: Input clock stopped
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
.DO(DO), // 16-bit output: DRP data output
.DRDY(DRDY), // 1-bit output: DRP ready
.LOCKED(LOCKED), // 1-bit output: LOCK
.PSDONE(PSDONE), // 1-bit output: Phase shift done
.CDDCREQ(CDDCREQ), // 1-bit input: Request to dynamic divide clock
.CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
.DADDR(DADDR), // 7-bit input: DRP address
.DCLK(DCLK), // 1-bit input: DRP clock
.DEN(DEN), // 1-bit input: DRP enable
.DI(DI), // 16-bit input: DRP data input
.DWE(DWE), // 1-bit input: DRP write enable
.PSCLK(PSCLK), // 1-bit input: Phase shift clock
.PSEN(PSEN), // 1-bit input: Phase shift enable
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement
.PWRDWN(PWRDWN), // 1-bit input: Power-down
.RST(RST) // 1-bit input: Reset
);
(2) The experiment and the simulation configuration instructions call parameter port portion
1 , parameter configuration instructions
In this study, the input clock CLKIN1 (150MHz) , to achieve the output feedback clock The CLKFBOUT (150MHz) , the output clock CLKOUT0 (74.25 MHz) , the output clock CLKOUT1 (74.25 MHz) , the output clock CLKOUT2 (59.4MHz) , the output clock CLKOUT3 (49.5MHz) . The key parameters are as follows
CLKFBOUT_MULT_F ( 1.98 ) // specified if different frequencies, then the associated CLKOUT clock output multiplier coefficient divided fraction. This figure CLKFBOUT_MULT_F and DIVCLK_DIVIDE combined value will determine the output frequency
DIVCLK_DIVIDE ( . 1 ) // specify all the division factor of the output clock relative to the input clock
CLKOUT0_DIVIDE_F (4), CLKOUT1_DIVIDE (4 ), CLKOUT2_DIVIDE (5), CLKOUT3_DIVIDE (6) // specified division factor of the frequency division outputs so that different output frequency
NOTE: Enter 150MHz multiplied by a multiplication factor of 1.98 , to obtain a frequency multiplier 297MHz , because DIVCLK_DIVIDE ( 1 ) is set to 1 , the frequency-divided reference clock is 297/1 = 297 ; feedback clock is also output: 297/1 = 297 ; then the other CLKOUT_DIVIDE_F , CLKOUT1_DIVIDE ~ CLKOUT6_DIVIDE dividing the divided reference clock binding according to the division ratio set 297MHz dependent, i.e. the reference clock frequency divider / corresponding frequency coefficient, such as where 297/4 ; 297/5 ; 297 / 6 . Simulation waveform which follows FIG. 1 shown
Figure 1
FIG 2 simulation waveform shown this is to change the parameter setting: DIVCLK_DIVIDE (2)
Figure 2
2 , port calls
MMCME4_ADV #(
.BANDWIDTH("OPTIMIZED"), // Jitter programming (HIGH, LOW, OPTIMIZED)
.CLKFBOUT_MULT_F(1.98), //
.CLKFBOUT_PHASE(0.0), //
.CLKIN1_PERIOD(6.6),
.CLKOUT0_DIVIDE_F(4), //
.CLKOUT1_DIVIDE(4),
.CLKOUT2_DIVIDE(5),
.CLKOUT3_DIVIDE(6),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.DIVCLK_DIVIDE(2), // Master division value (1-106)
.REF_JITTER1 (0.100)
)
MMCME4_ADV_inst (
// Clock Outputs outputs: User configurable clock outputs
.CLKOUT0(i_byte_clk), // 1-bit output: CLKOUT0
.CLKOUT0B(), // 1-bit output: Inverted CLKOUT0
.CLKOUT1(i_pix_clk74m25), // 1-bit output:
.CLKOUT1B(), // 1-bit output: Inverted CLKOUT1
.CLKOUT2(i_pix_clk59m4), // 1-bit output: CLKOUT2
.CLKOUT2B(), // 1-bit output: Inverted CLKOUT2
.CLKOUT3(i_pix_clk49m5), // 1-bit output: CLKOUT3
.CLKOUT3B(), // 1-bit output: Inverted CLKOUT3
// Feedback outputs: Clock feedback ports
.CLKFBOUT(mmcm_ser_ref_clk), // 1-bit output: Feedback clock
.CLKFBOUTB(), // 1-bit output: Inverted CLKFBOUT
// Status Ports outputs: MMCM status ports
.LOCKED(cmt_locked), // 1-bit output: LOCK
// Clock Inputs inputs: Clock inputs
.CLKIN1(clk150_g), // 1-bit input: Primary clock
// Control Ports inputs: MMCM control ports
.PWRDWN(1'b0), // 1-bit input: Power-down
.RST(i_ref_clk_rst) // 1-bit input: Reset
);
附：UltraScale+的高级混合模式时钟管理的三种原语库
MMCME3_ADV
The MMCME3 is a mixed signal block designed to support frequency synthesis, clock network
deskew, and jitter reduction. The clock outputs can each have an individual divide, phase shift
and duty cycle based on the same VCO frequency. Additionally, the MMCME3 supports dynamic
phase shifting and fractional divides.
MMCME3_BASE
The MMCME3 is a mixed signal block designed to support frequency synthesis, clock network
deskew, phase adjustment and jitter reduction. The MMCME3_BASE supports a subset of the
more common features and thus is easier to instantiate and use compared to the full features
MMCME3_ADV.
MMCME4_ADV
The MMCME4 is a mixed signal block designed to support frequency synthesis, clock network
deskew, and jitter reduction; The clock outputs can each have an individual divide, phase shif
and duty cycle based on the same VCO frequency. Additionally, the MMCME4 supports dynamic
phase shifting and fractional divides.