No glitches in the clock switching circuit is often in a test of a digital IC, but in the FPGA design, the basic clock gating rarely used this thing, and Xilinx also advisable to avoid re-gated design.
But I looked at night so many examples, mainly to seize the following three points:
1, clock selection signal terminal clock signal of a low level & ,, 2-stage register to play with two shot
2, the third stage of the register of the register output signal before two triggering edge of the clock, the sampling clock phase and then
3, say two or gated clock phase, the final output
