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All CDC related content in this blog: Cross-Clock Domain (CDC) Design Summary
1. Classification of cross-clock domain processing methods
The transmission of signals across clock domains may introduce metastability problems, so it is necessary to find a way to deal with them, thereby reducing the probability of metastability (ie, increasing MTBF).
Cross-clock domain processing methods can be divided into two categories: single-bit signal cross-clock domain processing, multi-bit signal cross-clock domain processing. The reason for the classification is that the transmission of multi-bit signals is not only the problem of metastability, but also may be due to the existence of signal transmission delay (skew) between multiple signals due to factors such as process and PCB layout, resulting in the signal being blocked. Missed or wrongly picked.
2. Combine multiple control signals
In the following example, the reading of data requires the load signal load and the enable signal en to be set at the same time, but there is a small skew (skew) between these two signals, when the single-bit cross-clock domain synchronization is performed respectively , due to the existence of the small skew, the two signals have a deviation of one clock cycle after being synchronized to the destination clock domain, and this deviation directly causes the data to be unable to be read.
Now ask yourself: Do both signals have to be delivered? In fact, it is not necessary. In the application, we can combine the two signals into one control signal, so that the cross-clock domain transfer of multi-bit signals is converted into the cross-clock domain transfer of single-bit signals. as follows:
3. Gray code
In the encoding of a set of numbers, if any two adjacent codes have only one binary digit different, this encoding is called Gray Code. In addition, because there is only one digit between the largest number and the smallest number Different, that is, "end-to-end", so it is also called cyclic code or reflection code. About the content of Gray code: Interconversion between Gray code and binary code implemented by Verilog
The following table shows the comparison of 4-bit natural binary code, 4-bit typical Gray code (no special instructions, typical Gray code is Gray code) and 4-bit decimal integer:
From the nature of the Gray code, we can find that although it is a CDC of a multi-bit signal, because only one adjacent bit is different each time, it is actually a CDC of a 1-bit signal. Good guy, it turns the problem into a familiar one Cross-clock domain problem of single-bit signal.
However, the application of Gray code also has limitations:
- Gray code only has a 1-bit change between adjacent two bits, which means that the data changes must be continuous (adjacent), that is to say, it is only suitable for continuously changing data, such as counters, which undoubtedly limits the Gray code. code application scenarios;
- The number of data transmitted by the Gray code must be 2 to the power of N----because only one digit is different between the largest number and the smallest number, that is, "end-to-end", so the Gray code is also called a cyclic code. If the number of Gray codes is not the N power of 2, "end-to-end connection" cannot be achieved, that is, when the last bit is passed to the initial bit, it will not only change by 1 bit, which undoubtedly goes against the original intention of using Gray code.
4. Handshake
The essence of the handshake method is negative feedback. Generally speaking, it is to first widen the CDC signal, then synchronize it to the destination clock domain, and generate an indication signal in the destination clock domain, which is used to indicate that the signal has been The clock domain is received, and then the indication signal is fed back to the source clock domain (feedback process). After the source clock domain receives this feedback signal, it will be pulled down by the CDC signal, thereby determining the stretch length. "This handshake completes a CDC transfer.
The picture above is a typical handshake process for CDC:
- The signal adt1 signal under the source clock domain aclk is the signal to be CDC;
- adt1 is first stretched under the source clock domain aclk, and then synchronized to the destination clock domain bclk through the two-stage synchronizer, which are bq1_dat and bq2_dat respectively;
- bq2_dat is used as an indicator signal (feedback signal, and a new indicator signal can also be generated through bq1_dat and bq2_dat), which is fed back to the destination clock domain aclk and synchronized, respectively aq1_dat, aq2_dat;
- The pull-up of aq2_dat indicates that the synchronization of the feedback signal is completed. At this time, adt1 can be pulled down (end the stretching process);
- After adt1 is pulled low (ends the stretching process), it indicates the end of a CDC operation.
The handshake method is a very safe method, but the disadvantage is also obvious: the timing overhead required is very large.
5. Asynchronous FIFO
There is no doubt that asynchronous FIFOs are the best and most common method for multi-bit signals to be processed across clock domains. Asynchronous FIFO controls the reading and writing of data at both ends in their respective clock domains through the first-in-new-out buffering mechanism, and the empty and full of data is indicated between the clock domains through the form of pointer + Gray code.
For asynchronous FIFO, please refer to:
Verilg implementation method of asynchronous FIFO
Regarding asynchronous FIFO design, you must understand these 7 points
6. DMUX synchronizer
For multi-bit data signals, enable technology can also be used, that is, an enable signal is used to determine whether the data signal is stable. When the enable signal is valid, it means that the data is in a stable state. In this case, the endpoint register is only Sampling the signal ensures that there are no setup/hold violations. The enable signal generally uses the double FF method to synchronize. The following is a schematic diagram of the synchronization of DMUX:
7. Other
- In the past, I usually posted code and simulation tests in my articles. I won't post this time, because I found a way without typing the code myself. This method will be written in the next article!
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