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All CDC related content in this blog: Cross-Clock Domain (CDC) Design Summary
1. What is cross clock domain?
The design of FPGA content is mostly based on synchronous circuits, and the triggering of synchronous circuits requires a unified clock. The clock signal seems to be the "heartbeat" of the circuit, providing blood to the "managed" flip-flops, and the signal under this clock signal can be called - belonging to the clock domain. With the improvement of chip integration and increasingly stringent design requirements, it is inevitable that the signal a originally belonging to clock domain A will appear in the embedded system or in the data interaction with other systems, which needs to be transmitted to another clock domain. B to operate on it, this operation is called cross clock domain, corresponding to Clock Domain Crossing, CDC.
Due to the difference in clock frequency and phase between the two parties, the synchronous signal a originally belonging to the clock domain A becomes an asynchronous signal in the clock domain B. We know that there is a probability that an asynchronous signal cannot meet the setup time and hold time requirements of the flip-flop. In the event of setup and hold violations, it is possible to cause the system to become metastable.
The basis of sequential circuits is flip-flops (FF, Flip-Flop). The normal operation of flip-flops needs to meet the timing requirements of setup time and hold time.
Set up time (Tsu: set up time)
It refers to the time that the data is stable before the rising edge of the clock signal of the flip-flop. If the setup time is not enough, the data will not be stably entered into the flip-flop on the rising edge of the clock. Tsu refers to this minimum stable time.
Hold time (Th: hold time)
It refers to the time when the data is stable after the rising edge of the clock signal of the flip-flop. If the holding time is not enough, the data cannot be stably entered into the flip-flop. Th refers to the minimum holding time.
2. What is metastable state?
Metastability : If the setup time requirements and hold time requirements of the flip-flop are not met during data transmission, metastability may occur. At this time, the output Q of the flip-flop is after the valid clock edge for a long period of time. In an indeterminate state, during which time Q is oscillating between 0 and 1, rather than equal to the value of data input D. This period of time is called the decision time Tmet (resolution time). After the resolution time, the Q terminal will stabilize to 0 or 1, but it will stabilize to 0 or 1, which is random and has no necessary relationship with the input.
As long as there are asynchronous components in the system, metastability is unavoidable, and metastability mainly occurs in common designs such as asynchronous signal detection, cross-clock domain signal transmission, and reset circuits. After the metastable state is generated, the output of the Q terminal of the register may be a burr, oscillation, or a fixed voltage value before it stabilizes. The metastable state in the signal transmission will cause other digital components connected to it to make different judgments, some judged to "1", some judged to "0", and some also entered the metastable state, the digital components will Logical confusion.
More references on setup, hold, and metastability: What exactly are "tapping (registered)" and "metastability" in FPGA design?
3. Classification of cross-clock domain processing methods
Since the cross clock domain of the signal may introduce the metastability problem, it is necessary to find a way to deal with it, thereby reducing the probability of metastability (ie, increasing the MTBF).
Cross-clock domain processing methods can be divided into two categories: single-bit signal cross-clock domain processing, multi-bit signal cross-clock domain processing . The reason for the classification is that the transmission of multi-bit signals is not only the problem of metastability, but also may be due to the existence of signal transmission delay (skew) between multiple signals due to factors such as process and PCB layout. Missed or wrongly picked.
4. Method for cross-clock domain processing of single-bit signal
After the signal crosses from the source clock domain to the destination clock domain, it needs to be operated under the "command" of the destination clock. This process can be regarded as "collecting" the processed signal with the destination clock. Since it is collection, it must be Satisfy the Nyquist sampling theorem, which means that the destination clock frequency needs to be at least twice the source clock frequency.
In the actual application process, not only the slow clock domain signal needs to be spanned to the fast clock domain, but also the fast clock domain signal needs to be spanned to the slow clock domain, and the latter obviously cannot satisfy the sampling theorem, so some specific processing is required.
4.1, level signal
If it is a level signal for CDC, no need to consider the speed of the clock, just use a 2-stage or other stage synchronizer, because it can always be sampled. In fact, the level model can be regarded as a super low frequency pulse signal.
4.2. Pulse signal from slow clock domain to fast clock domain
The first thing that needs to be agreed is that the so-called fast clock frequency should be at least twice the slow clock frequency. If it cannot be satisfied, the method 4.3 can be used for processing. Under this precondition, it can be ensured that the signal to be processed can be correctly collected by the destination clock domain.
Level 2 Synchronizer for Synchronization (DFF) is our most common approach to CDC handling. The essence of this method is to use flip-flops to synchronize the CDC signal to the destination clock domain, but metastable state may still occur in each synchronization. As the number of synchronization stages increases, the probability of metastable state will also decrease. Note that this process is not linear. In fact, the effect of reducing the metastability above the 3-stage synchronizer is very small. Usually a 2- or 3-stage synchronizer can be used to keep the probability of metastability at a very small value.
4.3. Pulse signal from fast clock domain to slow clock domain
In the figure below, adat is the pulse signal in the fast clock domain a, and bclk is the destination clock (slow clock). Obviously, the signal adat is missed after being synchronized to the destination clock domain, because the frequency of adat is higher than the destination clock. clock.
Since the frequency of the pulse signal is higher than the target clock, the missed sampling is caused, so if I widen the pulse signal to a certain extent, can it be guaranteed to be collected? The essence of this method is downscaling, that is, converting the problem to capturing a slower clock with a faster clock that we can already solve. As shown below:
After widening the signal adat to 3 times aclk, the pulse signal becomes a slower signal, and the destination clock becomes a faster clock, so we can use the 2-stage synchronizer method to synchronize the CDC signal. .
It should be noted that this method has certain limitations:
- If the two pulse signals to be synchronized are very close, the widening of the first pulse signal may cover the second pulse signal, resulting in the missed sampling of the second pulse signal;
- The widening of the pulse signal is based on the target clock, but if the frequency of the target clock is not known, this method may fail, that is to say, the method is not universal.
In order to explore a universal method, we can use the handshake method for CDC. The essence of the handshake method is negative feedback. Generally speaking, I will first stretch the CDC signal, then synchronize it to the destination clock domain, and generate an indication signal in the destination clock domain, which is used to indicate that the signal has been The destination clock domain receives, and then feeds back the indication signal to the source clock domain (feedback process). After the source clock domain receives this feedback signal, it will be pulled down by the CDC signal, thereby determining the stretch length, and also through "send--feedback-- Action "This handshake completes a CDC transfer.
The picture above is a typical handshake process for CDC:
- The signal adt1 signal under the source clock domain aclk is the signal to be CDC;
- adt1 is first stretched under the source clock domain aclk, and then synchronized to the destination clock domain bclk through the two-stage synchronizer, which are bq1_dat and bq2_dat respectively;
- bq2_dat is used as an indicator signal (feedback signal, and a new indicator signal can also be generated through bq1_dat and bq2_dat), which is fed back to the destination clock domain aclk and synchronized, respectively aq1_dat, aq2_dat;
- The pull-up of aq2_dat indicates that the synchronization of the feedback signal is completed. At this time, adt1 can be pulled down (end the stretching process);
- After adt1 is pulled low (ends the stretching process), it indicates the end of a CDC operation.
5. Others
- In the past, I usually posted code and simulation tests in my articles. I won't post this time, because I found a way without typing the code myself. This method will be written in the next article!
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