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Disclaimer: The following refers only to Xilinx Spartan6 series, does not necessarily apply to other FPGA.
FPGA design, the design of the system clock is extremely important, the clock signal will generally reduce the transmission delay of BUFG network, enhanced system performance and improve the stability of the system.
In actual use, often encounter ordinary IO output clock signal needs to be on a BUFG through the FPGA. If you connect directly from the BUFG to OBUF, errors will occur in the course of the compiler map and prompts avoid the wrong way is to add a constraint in the constraints file, let the compiler ignore the timing constraints of the requirements, directly through ordinary logic resources connected. Although this constraint can avoid this error, but the middle of the timing will not be assessed, which could lead to errors.
Xilinx Spartan6 solution for this application is given by ODDR2 connected, each IO has ODDR2 resources that can be connected to the network BUFG.
Example of use:
# ODDR2 (
.DDR_ALIGNMENT ( "NONE"), // Output Sets Alignment to "NONE", "C0" or "a C1"
.init (1'b0), // Sets The Initial State Q Output of or to 1'b0 1'b1
.SRTYPE ( "the SYNC") // Specifies "the SYNC" or "ASYNC" SET / RESET
) ODDR2_inst (
.Q (output clock signal requires connection), the DDR // output Data 'bit. 1-
.C0 (the BUFG clock signal on), // clock. 1 'bit-INPUT
.C1 (180 [degrees out of phase signal of the clock signal on the BUFG), // clock. 1' bit-INPUT
. CE (1'b1), //. 1 'bit-clock INPUT enable
.D0 (1'b1), //. 1 'bit Data-INPUT (Associated with C0)
.D1 (1'b0), //. 1' bit Data-INPUT (Associated with a C1)
.R (1'b0), RESET-INPUT 'bit. 1 //
.S (. 1'b0) // 1-bit set input
);
