Speaking in front of the UART, that is, one serial port module serial port module has two main components namely the baud rate clock generation module, where the need
Calculating the relationship between the system clock and the count value of the baud rate:
FPGA motherboard frequency is 50Mhz, T = 20ns
It refers to a 9600 baud 9600bps, 9600bit / s
then the period is 1 / rate = 1/9600 = 1.0416666667 * 10 ^ ( - 4) = 104167ns
Dividing the count value of the baud rate: 104167 / System_clk_period = 104167/20 = 5208
The relationship between the count value of the baud rate as shown in Table 1
| baud_set | Baud Rate | Baud rate period | Dividing the count value of the baud rate | The system clock count value 50M |
| 0 | 9600 | 104167ns | 104167/ System_clk_period | 5208-1 |
| 1 | 19200 | 52083ns | 52083/ System_clk_period | 2604-1 |
| 2 | 38400 | 26041ns | 26041/ System_clk_period | 1302-1211 |
| 3 | 57600 | 17361ns | 17361/ System_clk_period | 868-1 |
| 4 | 115200 | 8680ns | 8680/ System_clk_period | 434-1 |
Transfer: https://blog.csdn.net/liqiang9410/article/details/76682599