Verilog state machine transition conditions must be in a clock domain
problem
When designing a three-stage state machine recently, in the state transition part, signals in two clock domains are used as the conditions for state transition. Because the clock is not synchronized, the state switching is not ideal, resulting in the unstable state of the state machine, resulting in many very short states, which is not the expected result.
solve
The state transition conditions for the above problems use asynchronous FIFO prog_fullsignals and emptysignals.
As we all know, the asynchronous FIFO itself is used in the design of multi-bit data and clock domain, that prog_fullis , it is in the wr_clkclock domain, and the emptysignal is in the rd_clkclock domain.
In order that the state machine operates at the same clock domain, the design of the emptysignal at the wr_clktwo-shot clock domain Delay, so that the signal at wr_clka stable clock domain, then converted to a conditional access state FSM.
to sum up
When designing the Verilog state machine, the state transition condition must be in a clock domain, and the cross-clock AND transition can be performed in the form of a two-level D flip-flop .
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