Examples of timing constraints RGMII

RGMII interfaces:

https://blog.csdn.net/kemi450/article/details/91388581

RGMII interface constraints:

Here, an example has been 125MHz clock, clock and PHY configuration data phase shifted 90 °.

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The receiving end :

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1. Create an input clock and virtual clock. Wherein the virtual clock to describe the input delay.

   create_clock -name {rgmii_rxclk} -period 8.000 -waveform { 2 6 } [get_ports {rgmii_rxclk}]
   create_clock -name {rgmii_rxclk_virtual} -period 8.000

2. Input delay constraint. . Here, since the data and clock traces of the same, so that almost the same retardation.
   -clock set_input_delay [get_clocks rgmii_rxclk_virtual] -max 0.5 [get_ports "rgmii_rxd rgmii_rxctl *"] -add_delay
   set_input_delay-clock [get_clocks rgmii_rxclk_virtual] -min -0.5 [get_ports "rgmii_rxd rgmii_rxctl *"] -add_delay

3. 设置非关联路径。
   set_false_path -fall_from [get_clocks rgmii_rxclk_virtual] -rise_to [get_clocks rgmii_rxclk] -setup
   set_false_path -rise_from [get_clocks rgmii_rxclk_virtual] -fall_to [get_clocks rgmii_rxclk] -setup
   set_false_path -fall_from [get_clocks rgmii_rxclk_virtual] -fall_to [get_clocks rgmii_rxclk] -hold
   set_false_path -rise_from [get_clocks rgmii_rxclk_virtual] -rise_to [get_clocksrgmii_rxclk] -hold

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The sender

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1. Create a transmit clock. Here, 125MHz clock generated by the PLL, the output c0.
   -source -name rgmii_txclk create_generated_clock [get_clocks {fpga_pll_inst | altpll_component | PLL | CLK [0]}] \
   [get_ports rgmii_txclk {}] -PHASE 90

2. 约束输出延迟。 和。同理，时钟延迟和数据延迟一致。
   set_output_delay -clock rgmii_txclk -max  1.0 [get_ports "rgmii_txd* rgmii_txctl"] -add_delay
   set_output_delay -clock rgmii_txclk -max  1.0 [get_ports "rgmii_txd* rgmii_txctl"] -clock_fall -add_delay
   set_output_delay -clock rgmii_txclk -min -0.8 [get_ports "rgmii_txd* rgmii_txctl"] -add_delay
   set_output_delay -clock rgmii_txclk -min -0.8 [get_ports "rgmii_txd* rgmii_txctl"] -clock_fall -add_delay

3. 设置非关联路径。
   set_false_path -fall_from [get_clocks {fpga_pll_inst|altpll_component|pll|clk[0]}] -rise_to [get_clocks rgmii_txclk] -setup
   set_false_path -rise_from [get_clocks {fpga_pll_inst|altpll_component|pll|clk[0]}] -fall_to [get_clocks rgmii_txclk] -setup
   set_false_path -fall_from [get_clocks {fpga_pll_inst|altpll_component|pll|clk[0]}] -fall_to [get_clocks rgmii_txclk] -hold
   set_false_path -rise_from [get_clocks {fpga_pll_inst|altpll_component|pll|clk[0]}] -rise_to [get_clocks rgmii_txclk] -hold

4. Preferably the output clock output DDIO or DDR.