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edge-aligned sampling
The edge-aligned sampling method implements input delay constraints. As introduced in the eighth lecture of the series, in the case of edge-aligned sampling, it is easy to have insufficient hold time margin. This is because the next clock of the transmit clock is used as the sampling clock. When sampling data, due to the interval of one clock cycle, it is easy to cause the time of the sampling clock to be later than the time of the end of the data, so that the sampling clock cannot sample the data. You can use PLL alignment to make timing constraints, and use PLL to perform timing control on the clock. Shifting to the left advances the clock, which in turn increases the hold time margin.
Timing diagram
What happens if you use the PLL to shift time to the right? Verify it with specific experiments.
Change PLL parameters
It is still the previous experimental project, only need to change the parameters of the PLL IP core.
Change the Phase Offset to 60 and leave the rest of the parameters the same.
Integrated wiring
Open the routing design after the general routing is complete
report timing
Set as shown below
At this time, you can see that there is a violation of the establishment time.
path analysis
Click on one of the paths to analyze
From the timing report of this path, we can see that the column of requirement means that the sending clock is ons, and the sampling clock is 3.086ns. This is obviously a wrong analysis! A clock cycle is about 18ns, which is partially offset. The sampling clock should be about 20ns. It should be that the timing analysis tool mistakenly thinks that the sampling clock is the transmission clock just after the offset. What should I do?
Two Constraint Models
first model
This timing model can be used when the input has a PLL and the core does not have a PLL. When the phase shift of the sampling clock is positive with a PLL, a "multicycle constraint" needs to be performed, otherwise the analysis report will be incorrect. That is, when we phase-shift the clock to the right, we need to tell the timing analysis tool which sampling clock we want.
Actual operation
Click to edit timing constraints
Click to set multicycle path
add constraints
Set the specify path multiplier to 2, 2 means we need the second rising edge as the sampling clock.
path analysis
Click ok and reload to see the new timing report. You can see that the setup time is back to normal at this time, but the hold time is violated. You can click on one of the paths for analysis.
Still looking at the data in the requirement column, it means that the sampling clock was originally 18.518ns, but now it has become 21.604ns, which is consistent with the result we obtained by shifting the clock to the right. Although the hold time is violated, the correct timing is reported. Therefore, the multicycle constraint is required when the phase shift of the sampling clock is positive.
second model
This type of model uses the previous clock as the transmit clock and the next clock as the sampling clock. Compared with the previous model, the clock is equivalent to nearly one clock ahead. This timing model can be used when the input does not have a PLL. The routing tools are urged to increase the clock routing delay as much as possible so that the settling time meets the requirements, while the previous model was to make the clock routing shorter.
Simulate both models with real engineering (without PLL)
The experimental project is still modified from the previous one, and only the instantiation code of the PLL needs to be commented in the top layer.
top level code
module top_ioddr(
input wire rx_clk,
input wire rx_ctrl,
input wire [3:0] rx_dat,
//tx
output wire tx_clk,
output wire [3:0] tx_d,
output wire tx_dv,
input wire sdrclk,
input wire [3:0] sdrdata,
input wire sdrden,
output reg tout
);
wire rst;
wire rx_clk_90;
wire rx_en;
wire [7:0] rx_data;
reg tx_en1,tx_en2;
reg [7:0] tx_data1,tx_data2;
assign rst =0;
assign rx_clk_90 = rx_clk;
always @(posedge rx_clk_90 or posedge rst) begin
if (rst == 1'b1) begin
tx_data1 <= 'd0;
end
else if (rx_en == 1'b1) begin
tx_data1 <= rx_data+ rx_data -1;
end
end
always @(posedge rx_clk_90 or posedge rst) begin
if (rst == 1'b1) begin
tx_data2 <= 'd0;
end
else if (tx_en1 == 1'b1) begin
tx_data2 <= tx_data1+ tx_data1 -5;
end
end
always @(posedge rx_clk_90 ) begin
tx_en1 <= rx_en;
end
always @(posedge rx_clk_90 ) begin
tx_en2 <= tx_en1;
end
iddr_ctrl inst_iddr_ctrl
(
.rx_clk_90 (rx_clk_90),
.rst (rst),
.rx_dat (rx_dat),
.rx_ctrl (rx_ctrl),
.rx_en (rx_en),
.rx_data (rx_data)
);
oddr_ctrl inst_oddr_ctrl
(
.sclk (rx_clk_90),
.tx_dat (tx_data2),
.tx_en (tx_en2),
.tx_c (rx_clk_90),
.tx_data (tx_d),
.tx_dv (tx_dv),
.tx_clk (tx_clk)
);
reg [3:0] sdrdata_r1,sdrdata_r2;
reg sdrden_r1,sdrden_r2;
always @(posedge sdrclk) begin
{sdrdata_r2,sdrdata_r1} <= {sdrdata_r1,sdrdata};
end
always @(posedge sdrclk) begin
{sdrden_r2,sdrden_r1} <= {sdrden_r1,sdrden};
end
always @(posedge sdrclk) begin
if(sdrden_r2 == 1'b1) begin
tout <= (&sdrdata_r1)|(&sdrdata_r2);
end
else begin
tout <= (^sdrdata_r2);
end
end
endmoduleRe-wire the project
Open routing settings
Add clock constraints
set input delay
The maximum is 20.518ns and the minimum is 16.518ns, respectively. The setting method is basically the same as the previous tutorial.
There is a timing violation at this time
A violation of the setup time indicates that the next clock is too early relative to the start of the data, resulting in a violation of the setup time. In this model, it is hoped that the timing constraint tool can route the clock longer, so that the setup time can be longer. It's a bit larger, but it can't, so another constraint can be added to get the timing back to normal.
Solution
Constrain the timing to the model shown in the figure below
input delay constraint
The maximum is 2ns and the minimum is -2ns, which is equivalent to using the current clock as the transmit clock and the next clock as the sampling clock.
Integrated wiring
result
And report timing, you can find that the timing has returned to normal
Summarize
When there is a PLL constraint, both models can be used, but it should be noted that when the clock is shifted to the right, an additional "multicycle" constraint needs to be added. In order to save this part of the operation, the left shift is generally used. Constraint method of the clock.
In the absence of PLL constraints, we need to consider that if we need to make the data path routing longer (or make the clock path routing shorter), we can use the first model for constraints; if we need to make The clock path routing is longer (or the data path routing is shorter), which can be constrained using the second model.
Past series of blogs