1. Main clock constraints
The master clock is usually the board clock external to the FPGA device or the synchronous recovery clock signal of the FPGA's high-speed transceiver output data, etc. The following grammar must be familiar to everyone. This statement is used to constrain the name, period, duty cycle and corresponding physical pins of the main clock.
create_clock -name <clock_name> -periood <period> -waveform {
<rise_time> <fall_time>} [get_ports <port_name>]
In a design, unconstrained clocks can be viewed through the Clock Network Report and Clock Acknowledgment Report. After opening the synthesis and implementation design, enter the following command:
report_clock_networks
check_timing
For constraining the output clock network of the high-speed transmitter (gt) as the master clock, the command is as follows:
creat_clock -name rxclk -period 6.667 [get_nets gt0/RXOUTCLK]
For the output clock pin of some hardware primitives, if there is no strong causal correlation with its input clock, the output pin of this hardware primitive can also be used as the clock source for master clock constraints.
For differential clocks, only the main clock constraints need to be imposed on the input positive terminal (sys_clk_p) of the differential buffer. If the positive and negative terminals are constrained at the same time, unreal CDC (clock domain crossing) paths will be generated.
For MMCM and PLL, the system will automatically generate the corresponding constraint files, no manual constraints are required.
In some timing paths, such as data signals on some pins, the synchronization clock only exists in the external chip and does not exist in the FPGA device. In this case, for the needs of timing analysis, a clock must also be defined to describe the external clock signal of the timing data pin. This clock is the virtual clock. No pins are required for virtual clock constraints.
create_clock -name clk_virt -period 10
2. Clock characteristic constraints
There are two constraints on clock jitter. Set_input_jitter can only constrain the main clock, and set_system_jitter defines system jitter.
set_input_jitter [get_clocks <clock_name>] <jitter_in_ns>
set_system_jitter <clock_name> <jitter_in_ns>
All factors that may affect the clock periodic deviation except clock jitter can be defined using the set_clock_uncertainty command. Also called user uncertainty.
set_clock_uncertainty -<setup/hold/空出来表示两者都有> -from [get_clocks <clock0_name>] -to [get_clocks <clock1_name>] <uncertainty_value>
For clock delay constraints, there are the following commands:
set_clock_latency [-clock <args>] [-rise] [-fall] [-min/max/空出来表示两者都有] [-source] <latency> <objects>
3. Derived clock constraints
Derived clocks mainly refer to clock signals generated by dividing, multiplying or phase shifting the existing master clock, such as clock signals driven by MMCM or some design logic. Generally, Vivado's timing tools can automatically generate the correct derived clock. If the designer thinks that the automatically generated derived clock is wrong, he can also manually constrain the derived clock.
create_generated_clock -name <generated_clock_name> -source <master_clock_source_pin_or_port> -multiply_by <mult_factor>\
-divide_by <div_factor> <pin_or_port>
4.IO interface constraints
The timing constraints of the IO interface mainly include set_input_delay and set_output_delay. The input and output constraints are similar. The main constraints are as follows:
set_input_delay -clock<args> -reference_pin<args> -clock_fall -rise -max -add_delay <delay> <objects>
#下面对命令进行解释
-clock 用于指定约束引脚的同步时钟（源时钟），其后的<args>即需要指定的同步时钟名称，这个时钟可以是设计中事先定义的主时钟或虚拟时钟。
-reference_pin 用于指定延时值<delay>的参考时钟，其后的<args>即需要指定的参考时钟名称。该项是可选项，不指定该选项，则指定延时值的参考时钟就是-clock指定的同步时钟。
-clock_fall 指定输入延时约束取值相对于同步时钟的下降沿。若不指定，默认为-clock_rise
-rise 指定约束信号相对时钟的边沿关系是上升沿，也可以用-fall指定为下降沿
-max 设定最大延时值，也可以是-min最小值。若不指定，则是最大最小值都包括
-add_delay 用于多组参考组合的输入引脚约束
<delay> 设定延时值
<objects> 指定约束的目标输入引脚名称
The calculation of input delay is as follows:
set_input_delay(max)= -Tc2j_pcb(min) + Tco(max) + Td_pcb(max)
set_input_delay(min)= -Tc2j_pcb(min) + Tco(max) + Td_pcb(min)
其中c2j_pcb代表时钟源在pcb上的走线延时，d_pcb为数据在pcb上的走线延时，co为外部芯片数据引脚输出数据所经过的延时，查芯片手册可以获得。
set_output_delay(max)= Td_pcb(max) - Tc2j_pcb(min) + Tsu
set_output_delay(min)= Td_pcb(min) - Tc2j_pcb(min) - Th
5. Clock exception constraints
Reasons for timing exception constraints: The default timing check method of the timing analysis tool may not be consistent with the actual situation of the project implementation (usually the constraints are too tight, which may lead to timing failure). Therefore, designers need to add some additional constraint commands to adjust the existing timing check methods to ensure that the timing check of the timing tool is consistent with the actual situation.
Typical examples of timing exception constraints: 1. Asynchronous clock domain paths, usually using clock grouping constraints or false path constraints and multi-cycle constraints. 2. Some logical sequential units do not perform data sampling and transmission in every clock cycle. In this case, multi-cycle constraints can be used to appropriately relax the constraints on these paths. 3. Sometimes in the design, it is desired to impose tighter constraints on the timing path to obtain greater timing margin. In this case, maximum/minimum delay constraints can be used. 4. Some combination paths are static (the assignment does not change) or do not require timing constraints. In this case, false path constraints can be used to ignore these paths.
5.1 Multi-cycle constraints
The multi-period constraint syntax is as follows:
set_multicycle_path <path_multiplier> -setup/hold -start/end -from <startpoints> -to <endpoints> -through <pins/cells/nets>
#
-start和-end用于指定约束命令的周期参数是以源时钟还是以目标时钟作为参考时钟。
For timing path analysis where the source clock and target clock are of the same frequency and phase, there is no difference whether -start and -end are used.
The number of clock cycles of the hold time = the <path_multiplier> parameter of the setup time - 1 - the <path_multiplier> parameter of the hold time. Under normal circumstances, if only the set_multicycle_path constraint is applied to the setup, the <path_multiplier> parameter of the hold time defaults to 0, that is, the default number of clock cycles of the hold time is one clock cycle different from the <path_multiplier> parameter of the setup time. Then if only the setup is constrained, the relationship between the establishment time and the hold time will move to the right at the same time by the <path_multiplier> parameter - 1 clock cycle. If the <path_multiplier> parameter constraint is added to the hold, the hold time relationship will move to the left by the hold. <path_multiplier> parameters clock cycles to achieve the effect of multi-cycle constraints.
A diagram is given below.
When the constraint is only set_multicycle_path 2 -setup -from [get_pins data0_reg/C] -to [get_pins data1_reg/D], the graph is as follows:
When the constraint is set_multicycle_path 2 -setup -from [get_pins data0_reg/C] -to [get_pins data1_reg/ D] and set_multicycle_path 1 -hold -from [get_pins data0_reg/C] -to [get_pins data1_reg/D], the graph is as follows: <a i=5> For clocks with the same frequency and out-of-phase, by default the timing tool will look for the rising edge of the clk2 clock that is adjacent to clk1, and use the one with the shortest relative time between clk1 and clk2 (the highest timing requirement, that is, the worst case) A set of clock edge timing paths are analyzed. At this time, use the following constraint command to make adjustments:
set_multicycle_path 2 -setup -from [get_clocks CLK1] -to [get_clocks CLK2]
For the slow clock domain to the fast clock domain or the fast clock domain to the slow clock domain, there are different approaches but the same purpose. What needs to be paid attention to is the confirmation of -start and -end. The general constraint methods for these two situations are given below.
#慢-快
set_multicycle_path N -setup -end -from [get_clocks CLK1] -to [get_clocks CLK2]
set_multicycle_path N-1 -hold -end -from [get_clocks CLK1] -to [get_clocks CLK2]
#快-慢
set_multicycle_path N -setup -start -from [get_clocks CLK1] -to [get_clocks CLK2]
set_multicycle_path N-1 -hold -start -from [get_clocks CLK1] -to [get_clocks CLK2]
5.2 False path constraints
The so-called false path means that the path is a non-functional path in the design or a path without any timing requirements. The reason for making false path constraints: it can reduce compilation time and free up limited placement and routing resources to improve overall timing performance. Common false paths include: 1. Cross-clock domain paths that have been synchronized. 2. Only initialize and write the register path once after power-on. 3. Reset or test the logic path. 4. Certain timing paths that do not actually exist. For example, if the data communication between two asynchronous domains in the design has been synchronized using a method such as dual register latching, a false path constraint can be used to turn off the data path checking between the two clocks. The basic syntax of constraints is as follows:
set_false_path -setup/hold -from <node_list> -to <node_list> -through <node_list>
#对于两个或多个相斥时钟做约束推荐用法
set_clock_groups -group CLKA -group CLKB
5.3 Maximum/minimum delay constraints
The maximum delay constraint will override the default setup time analysis maximum path delay value. The minimum delay constraint will override the default minimum path delay value for hold time analysis. The basic constraint syntax is as follows:
set_max_delay <delay> -datapath_only -from <node_list> -to <node_list> -through <node_list>
set_min_delay <delay> -from <node_list> -to <node_list> -through <node_list>
Among them, -datapath_only can only be used in the set_max_delay constraint command containing the -from option. This option will remove clock skew consideration and set the hold time check of the constraint path to the false path, which is equivalent to automatically generating a set_false_path -hold constraint for this path. In other words, if the set_min_delay constraint is applied to the same path, it will be ignored.