Timing constraints (2)

Timing Constraints (2) The
previous article gave an overview of the principle of timing constraints, and it was also explained more clearly on the Internet, or the videos of Xiaomei and You Kaiyuan on the Internet were very good. Here is mainly an overview of the principle. It is to do some practical exercises, or the situation encountered in the project at hand.
The project at hand is high-speed AD data acquisition, 300M sampling clock, DDR data transmission mode, which means that the clock cycle is 3.33ns, and the upper and lower edge sampling is equivalent to the clock cycle of only 1.667ns. The correct timing constraints are not performed here. It is possible that data cannot be collected normally. Here we first look at the situation of data collection without correct constraints or without constraints. As shown in the figure below:
1. When the timing is not constrained or wrongly constrained, the input signal 5M sine wave and square wave are as follows:


FPGA is sampled and saved in ram, and the result is displayed after being collected by DSP:


we can see that the input signal is not Glitch, but the collected signal has obvious glitches. The direct reason is that the timing is not correctly constrained. When data is collected on the rising and falling edges of the clock, the setup and hold time cannot be satisfied. That is, the data is unstable when the clock is sampled. Make changes. The schematic diagram is as follows:

It can be seen intuitively from the figure that what the timing constraint needs to do is to make the sampling edge of the clock fall in the stable area of ​​the data. How to make the clock sampling edge fall in the data stable area? The actual situation is that the clock and data have a delay in the propagation of the circuit. If the setup time is not satisfied, the clock delay can be larger, or the data delay can be made smaller, if the hold time is not satisfied, the clock delay can be made smaller , You can also make the data delay longer. Specific analysis of specific situations, such as modifying logic, increasing pipeline, adding phase-locked loop phase shift, input/output delay can also change the clock data phase relationship of external devices and other methods. All these methods are to make the clock sampling edge fall in the data stable area. We will analyze the actual examples and operations in detail later.
2. In the case of timing constraints, the input signal 10M sine wave and square wave are as follows:


FPGA is sampled and saved in ram, and the result is displayed after being collected by DSP as follows:


After FPGA sampling, ila directly grabs the data and displays the results as follows:


you can see that the burr of the waveform disappears after the correct timing constraint, the collected signal is consistent with the input signal, and the original input signal is basically restored. This is the subsequent signal processing The premise is that if the collected data is not correct, the calculation and processing of the data will not be discussed later.
This article mainly shows the importance of timing constraints through a timing constraint example. Later, we will use the operation of the vivado project example to learn more about how the vivado tool performs timing constraints.