1. Basic concepts of timing analysis
1. Clock
A rational clock model is a square wave with a duty cycle of 50% and a fixed period:
In the actual circuit, the crystal oscillator clock signal input to the FPGA is a sine wave:
2. Clock jitter
Clock Jitter, clock jitter, relative to the ideal clock edge, the actual clock has an offset that is not accumulated with the clock, sometimes leading and sometimes lagging.
3. Clock skew
Clock Skew: Clock deviation, the difference in the time it takes for clock signals in the same clock domain to reach various parts of the digital circuit.
4. Setup time and hold time
Setup time, Setup Time, Tsu, the minimum time that data must be stable before the rising edge of the clock. If the setup time is not met, data cannot enter the register, and the data sampling of the register will fail.
Hold time, Hold Time, Th, the minimum time that data must be stable after the rising edge of the clock. If the hold time is not met, the data cannot enter the register, and the data sampling of the register will also fail.
5. Initiating edge and sampling edge
rega and regb use the same clock signal. rega sends data at the Launch Edge. The Capture edge of the next clock cycle of regb samples the data sent by rega. There may be some combinational logic between reag and regb.
2. Basic formulas of timing analysis
1. Basic path of timing analysis
The basic paths of timing analysis include:
(1) The path between pin input and register (pin2reg)
(2) Register and path between registers (reg2reg)
(3) The path between register and pin output (reg2pin)
(4) The path between pin input and pin output (pin2pin)
2. Data arrival time and clock arrival time
(1) Data Arrival Time
After the data is sent on the sending edge, how long does it take to arrive at the data port of the receiving register, that is, the time it reaches the D port of regb.
(a) The launch edge is usually selected as the zero time reference point
(b) The data reaches the Q port after Tco time.
(c) Data from the Q port must go through combinational logic and wiring delays before reaching the D port at the receiving end.
3. Setup time margin
Setup time margin, Setup slack
A positive value for the establishment margin indicates that the two registers have a qualified establishment relationship. A negative value for the establishment margin indicates that the establishment relationship between the two registers is not satisfied, which will lead to sampling errors.
The time for data to arrive at the D end of reg2 is:
Starting edge time+Tclk1+Tco+Tdata
= 0 ns + 3.2ns + 0.2ns + 0.6ns
= 4ns
reg2 can ensure that the sampling is correct and the time when the required data arrives
Tclk + Tclk2 - Tsu
= 10ns + 2ns - 1.4ns
= 10.6ns
Create margin:
Setup Slack = Data Required Time - Time Arrival Time
= 10.6 ns - 4 ns
= 6.6 ns
4. Keep time margin
Maintain time margin, Hold Slack
A positive value of the holding margin indicates that the two registers have a qualified holding relationship. A negative value of the holding margin indicates that the holding relationship of the two registers is not satisfied, which will also lead to sampling errors.
Data Hold TimeData Hold Time
= Start edge + Tclk1 + Tco + Tdata + data cycle time
= 0 ns + 3.2 ns + 0.2 ns + 0.6 ns + 10 ns
= 14 ns
Data latch timeData Required Time
= latch edge + Tclk2 + Th
= 10 ns + 2 ns + 1.4 ns
= 13.4 ns
Hold Slack
= 14 ns - 13.4 ns
= 0.6 ns