FPGA timing analysis and common methods of timing constraints (part 2)

Common timing optimization methods are:

1: The critical path is inserted into the register.
This problem is easy to occur when there is too much combinatorial logic in a piece of code.
2: Double beat
When the data interaction between modules involves cross-clock domains, the double beat can usually be used. This is a very useful way to avoid metastability

    reg    [7:0]data_reg1;
    reg    [7:0]data_reg2;
	
    always@(posedge clk_50M or negedge rst_n)  	
	    if(!rst_n)
		    data_reg1 <= 8'b0;
		else
		    data_reg1 <= data;
	
	always@(posedge clk_50M or negedge rst_n)
	    if(!rst_n)
		    data_reg2 <= 8'b0;
		else
		    data_reg2 <= data_reg1;

3: Avoid one module to drive multiple modules.
This is considered from the framework of module design. If you really want to use one module to drive multiple modules, you can consider instantiating this module multiple times to achieve more consumption. Hardware resources in exchange for better timing