Collection of articles about timing constraints

Collection of articles about timing constraints

Recently, I have been sorting out Vivado's programs, regarding the issue of timing constraints;

The written program, modelsim RTL level simulation are logical, but after the compilation is downloaded to the board, a series of problems will appear.

Most of them are due to timing constraints;

Previously, there were relatively few concepts of timing constraints. It was obviously not enough to know only some master clock constraints. Therefore, I was crazy to find vivado-related timing constraints on the Internet. I have found a lot of them. First, comprehensively record and collect them.

Collection of timing constraint articles

Related articles on FPGADesigner :

• Vivado Skills (29): Overview of Constraint Function

• Vivado use skills (30): use the timing constraint wizard

• Vivado use skills (31): clock constraint method

• Vivado Use Skills (32): Constraint Method of IO Delay

• Vivado use skills (33): abnormal timing

• Vivado use skills (34): path segmentation phenomenon

Related articles of zhanghaijun2013 :

• 1 Set-up and hold time of FPGA Timing Constraint Theory
• 2 Timing path and timing model of FPGA Timing Constraint Theory
• 3 IO constraints of FPGA Timing Constraint Theory
• 4 Clock Cycle Constraints in FPGA Timing Constraint Theory
• 5 Two timing exceptions in FPGA Timing Constraint Theory
• 6 xdc constraint priority of FPGA timing constraint theory
• 7 FPGA Timing Constraint Actual Combat: Sorting out the Clock Tree
• 8 Master Clock Constraints in FPGA Timing Constraints Actual Combat
• 9 Derivative Clock Constraints of FPGA Timing Constraint Practical Chapter
• 10 Delay Constraints in FPGA Timing Constraint Practical Chapter
• 11 Pseudo path constraints in FPGA timing constraints actual combat
• 12 FPGA Timing Constraint Practical Chapter of Multi-cycle Path Constraints
• 13 Vivado auxiliary tools for FPGA timing constraints
• 14 Objects and attributes of Tcl commands for FPGA timing constraints

This series of articles is very detailed, and there are also corresponding B station videos:

FPGA Timing Constraint Tutorial

After taking a look at the above tutorials, the current timing constraints of the project will no longer report violations, and we need to take a closer look.