I believe that many people have more or less heard of the concept of timing constraints after coming into contact with FPGA; they have also seen many timing constraint tutorials, but most of them are general and theoretical, and few tutorials will tell you, For a certain tool, how should we set timing constraints. What's more, some people confuse timing constraints and timing analysis, which makes people more confused.
1. Timing constraints and timing analysis
So, to explain timing constraints clearly, I think it is necessary to first explain what timing constraints are? What is the relationship between timing constraints and timing analysis?
Constraint, constraint, what is constraint? In addition to timing constraints, there are also physical constraints, right? So what are physical constraints for? Our basic physical constraints include pin position constraints and level constraints. So it is not difficult to see from here that the so-called constraints are a way for us to tell the tool our design information. Physical constraints inform the pin position and level (of course there are also some high-order physical constraints that can fix the position of the BRAM/DSP core). Timing constraints, as the name implies, inform the tool of information such as frequency, duty cycle, IN/OUT delay, etc. The timing conditions of our design.
Besides, what does timing constraints have to do with timing analysis?
Many people have probably seen this static timing analysis model;
I followed others around and did the math, but in the end I didn't figure out how to do timing constraints. After running through it, there are a lot of "popular" timings that I don't know how to solve. Based on the attitude that it can be used, I just let it go and wait for the next person. So what exactly is timing analysis? To put it simply, timing analysis is a step for tools to check whether the design meets timing requirements; so there is an important point here. Timing analysis is performed by tools, not engineers. Engineers only need to know the principles of its analysis and know when timing "explodes". ” direction of improvement. Then, the tool is used to analyze the standard of whether the timing requirements are met. This standard is the timing constraint. Therefore, making timing constraints can also be understood as informing the tool of our timing goals. This requirement is not the stricter, the better, nor the looser, the better; accuracy is the most important .
2. Contents of timing constraints
In fact, different tools have different constraints. For example: ISE looks at the problem from the perspective of FPGA. It will think that all default constraints between clocks are asynchronous and will not actively perform timing analysis (unless it is constrained to be synchronous in advance); while Vivado is completely opposite, Vivado By default, all clocks are synchronized unless specified in advance. There are no exception constraints or clock groupings. The tool will actively analyze each cross-clock domain path. This is also the reason why many people complain about the slow comprehensive implementation of Vivado after switching from ISE to Vivado; look at the "hot" path and see if there are any unreasonable requirements of "requirement = 0.x". This is obviously because the timing constraints are not set correctly. s reason.
So what timing constraints do we need to set for Vivado? This is only a brief introduction, and will be introduced in subsequent articles.
1. Clock constraints:
create_clock
Set input clock constraints, including crystal oscillator input and GTX input; the most important thing is to set it at the earliest ;
create_genarate_clock
Set derived clock constraints
set clock group
Set clock groups to inform tools about the asynchronous and synchronous relationships of each clock
2. IO constraints:
set input/output delay
set max/min delay
By default, Vivado will default to infinite timing requirements for IO constraints. The comprehensive implementation will not consider I/O timing optimization, and unconstrained paths will not be "popular" during timing analysis.
3. Exception constraints
set false path
Pseudo path constraints tell the tool not to analyze the path;
set multicycle
Multi-cycle constraints, relax timing analysis conditions, but not completely eliminate analysis;
3. How to perform timing constraints in Vivado
1. It is recommended to constrain through Constraints Wizard
2. Directly write XDC files for constraints through the templates in Tool --> language Templates --> XDC