Recently received a project that uses K7 Gigabit network functionality through RGMII. vivado with IP in the core SGMII, RGMII interfaces need to write a GMII and RGMII converter (zynq series with GMII turn RGMII IP core). K7 provided IDDR and ODDR primitives can be achieved RGMII to GMII GMII and converted to RGMII, respectively. Then the data to the UDP, to achieve the parsed data. Each sending and receiving UDP interfaces by one the FIFO, buffer for data to improve the efficiency of the transceiver. PHY chips use 88E1512. Gigabit network shown as a block diagram.
RGMII interfaces Introduction
RGMII interfaces:
RGMII i.e. Reduced GMII, RGMII is a simplified version of the interface signal lines to reduce the number from 24 to 14 (COL / CRS port status indication signal, not shown here), the clock frequency is still 125MHz, TX / RX data width from 8 is changed to four, in order to maintain the transmission rate unchanged 1000Mbps, RGMII sampled data interfaces in rising and falling edges of the clock. The GMII interface to transmit TXD [3: 0] on the rising edge of the reference clock / RXD [3: 0], transmit GMII interface on the falling edge of the reference clock TXD [7: 4] / RXD [7: 4]. RGMI also compatible 10Mbps and 100Mbps two rates, then the reference clock rate of 25MHz and 2.5MHz, respectively.
| RXD(Receive Data)[3:0] | Receiving data signals, a total of four signal lines |