Background: Timing analysis and timing constraints are a very basic but important part of the FPGA. Designing a good timing circuit is not a simple matter. To understand what is the timing analysis and timing constraints of the FPGA, we must first have a certain understanding of the basic composition of the FPGA development board.
Here you can simply divide the FPGA chip into three parts
1: Fast programmable logic function
It can be said that without considering the price, the number of programmable logic function blocks is a very important factor for us to buy an FPGA development board. The full name of FPGA is Field Programmable Gate Array . The scene here refers to two mainstream FPGA manufacturers, Altera and Xilinx. Most of their FPGAs are based on SRAM technology, so they can be erased and written repeatedly. The programmable logic function block we are talking about here can be understood as the basic unit to realize the function of FPGA programmable .
The programmable logic function is quickly divided into three parts
1: Look up table (LUT for short)
In our hardware description language Verilog or VHDL, the combinatorial logic in the code is implemented through the search It is implemented in the form of a table, and the output will be different according to different input lookup tables. We often hear about four-input lookup tables, six-input lookup tables, and so on.
2: Flip-flop (abbreviated as FF, commonly used D flip-flop is DFF) The
essence of FPGA is the physical realization of digital circuit, so the flip-flop mentioned here is the same as in our digital circuit. The simplified schematic diagram of D flip-flop is as follows, When the reset signal is invalid, the flip-flop starts to work normally. Whenever the clock edge comes, the data is sent from the D port to the Q port. (This is the basis for our subsequent understanding of timing analysis and timing constraints)
3: Carry chain
2: Chip interconnection line
3: IO port
In addition to the above three resources, FPGA chips generally have
1: Digital clock management unit
2: DSP (embedded hard-core divider)
3: High-speed serial I/O interface
4: Special function modules (PCIE, DDR, etc.) Hard IP)
5: Some with arm (that is, SOC architecture with PL + PS)
Common timing problems are divided into four categories:
1: register to register
2: input pin to register
3: register to output pin
4: input pin to output pin
Let's talk about some basic knowledge in timing analysis in conjunction with the structure diagram of the D flip-flop given above.
Timing analysis: Timing analysis analyzes the path of data from one register to the next register. What we analyze is the data transmission on this path to see if the data can be correctly received and sent to the next level Circuit.
Timing constraints: The purpose of timing constraints is to ensure that the time of the data on the above path is controlled within one clock cycle. Timing constraints What we want to do is to tell the EDA tools some of our design requirements, and then let the EDA tools to automatically optimize the placement and routing to meet our design requirements as much as possible.
The significance of timing analysis and timing constraints: It can be summarized in two points. The first is to ensure the correct acceptance of data. The second is to allow the circuit we design to run at a higher clock frequency. After all, FPGA is very important. The characteristic is that it can process data at a high speed. Of course, behind this is a higher frequency clock.
Setup time (setup_time): FPGA generally collects data on the rising edge of each clock. The setup time means that before the rising edge of a clock comes, the data should be prepared in advance, so that we can collect the data correctly, so We define the setup time as the minimum time that the data must remain stable before the rising edge of the clock
Hold time (hold_time): Similarly, let’s understand hold time. Hold time is to accept data correctly. It refers to the minimum time that data must remain stable after the clock edge is sampled.
Tco: The delay between data entering from the input port of the flip-flop and exiting from the output port. This delay is determined by the electrical characteristics of the device itself. Generally speaking, this time is very short.
Tdata: The delay time of data transmission. The length of this time depends entirely on the quality of your code. We often say that good timing is designed, but it actually refers to this part. Too long data transmission time is not conducive to satisfying the establishment time, but too short data transmission time is not conducive to satisfying the retention time