Static Timing Analysis Concise Tutorial (4)] Clock Conventional Constraints

STA's Clock General Constraints

1. Write in front

What is the core competence of a digital chip engineer ? Different engineers may give different answers. Some may refer to hardware description language , some may refer to understanding of specific algorithms and protocols , and some may refer to the combination of hardware and software . The author wants to say, These statements are actually correct or not. The hardware description language is nothing more than the repeated use of the statements always and assign, and some basic protocol algorithms are actually not complicated to study. For the author, in conventional skills In addition, there are two additional skills that are quite important, one of which is the analysis ability of sdc/STA , which is important as a bridge to establish the connection between the front end and the back end , although for DE engineers, the first version delivered sdc is often inaccurate, and there is no way to generate an error-free timing report through this sdc, but the content of sdc is a complete and complete mapping of timing constraints from behavior-level description to gate level, a real circuit level. above. Writing this column, one is for learning records, and the other is for communication and sharing , in order to reward fans and readers.

1.1 Quick Navigation Links ·

Second, the characteristics of the clock

First of all, we need to emphasize that the premise of our static timing analysis concise tutorial 4 is to design the circuit synchronously , and the static timing analysis of STA is invalid for asynchronous circuits.
Secondly, under the condition that we constrain the clock, we need to master the three characteristics of the clock, they are:

Period : Refers to the repeated action of a clock signal after a specific time has elapsed .
Valid edge : The clock edge is divided into rising edge and falling edge .
Duty Cycle : The percentage of the positive phase time in the total clock cycle.

3. create_clock

create_clock -period period_value
			 [source_objects]
			 [-name clock_name]
			 [-waveform edge_list]
			 [-add]
			 [-comment comment_string]

3.1 Define the clock period

The -period option is used to define the clock period . Usually, the unit of the clock signal is ns by default, but we can also set clock units such as ps through set_units.

create_clock -period 10

The above statement means that we set a clock signal with a clock period of 10ns , that is , a clock frequency of 100Mhz .

3.2 Identifying the clock source

When we determine the clock cycle, we also need to correspond the clock signal to a source object (such as a clk port, or a flip-flop pin P, network N), this step is like adding a The clock signal in STA is mapped to an object at the circuit level to be driven.
We can use the following statement to identify it

#代表作为时钟源端口
create_clock -period 10 [get_ports A]

#代表作为时钟源的网络
create_clock -period 10 [get_nets N]

#代表作为时钟源的引脚，若触发器的名称为FF的话
create_clock -period 10 [get_pins FF/P]

3.3 Naming the clock

When we map the port, the next problem is the name of the clock . If we do not specify the name separately, the tool will assign a default name to the clock. In the timing analysis of STA, the name of the clock is Important information because once a clock signal is defined and named, all other SDC commands that depend on this clock only need to mention that clock . We name the clock by the -name suffix, for example

#创建一个10ns的时钟，映射到端口A，时钟命名为PCLK
create_clock create_clock -period 10 [get_ports A] -name PCLK

3.4 Specifying the duty cycle

Here we can be a bit brief, because for digital circuits, the duty cycle is not a 1:1 circuit structure, and there are few types, but if we want to specify the duty cycle, we can use -waveform to do it, paste the information Address, interested readers can consult and learn
Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

3.5 Homologous Multiple Clocks

When we design a module, its working frequency is not fixed in many cases, such as a UART module, we may use it on the 200MHz APB bus, or we may use it on the 400M/1GHz APB bus , if this design needs to specify multiple clocks in the clock source to meet the needs of multi-IO speed protocols , we may need to add a suffix in the form of "-add" in the SDC to make the STA's All clocks can be considered in the process. If we don't add "-add", the latter clock signal may overwrite the previous one

#同时对CLK端口做100MHz和50MHz的时钟约束
create_clock -name C1 -period 10 [get_ports CLK]
create_clock -name C2 -period 20 [get_ports CLK] -add

3.6 Annotation Clock

In addition to using the comments in the tcl language, SDC also provides engineers with comment options. Using the -comment suffix, we can add the documentation information of the clock signal in the form of comments, such as:

#设定一个时钟信号，周期为10ns，信号名称为PCLK，映射到clk端口，备注为“Clock for UART input”
create_clock -period 10 -name PCLK 9get_ports clk] -comment "Clock for UART input"

3.7 Virtual Clock

The final concept is virtual clocks . As the name suggests, virtual clocks have no way to map to real port nets or pins , but their presence can help designers use more flexible clock characteristics (such as clock offsets, etc.) to check, The command is as follows:

#建立一个周期为10ns，名称为vclk，不映射到具体端口的时钟（虚拟时钟）
create_clock -period 10 -name vclk

4. Summary

In this article, we discussed the most basic command in STA analysis/SDC constraints - clock constraints, the specific content can be divided into some basic content such as creating clocks, naming clocks, commenting clocks, virtual clocks, and identifying clocks, while In the next section, we will discuss other characteristics of clock signals such as frequency division, frequency multiplication, gating, etc.