Although there are hundreds of commands in sdc, there are actually only 10 commonly used commands. Today we will introduce the commands related to the clock. There are mainly the following commands:
create_clock
create_generated_clock
set_clock_uncertainty
set_clock_groups
The first definition of any sdc is the clock. For a synchronous circuit, the path delay time between the buffer and the buffer must be less than one Clock cycle (Period), that is, when we confirm the Clock specification, all buffers The Timing Constraint of the path between them is automatically given. The Clock specification mainly includes the definitions of Waveform , Uncertainty and Clock group . We call them the three elements of the clock , of course, to create any clock, check whether these three are correctly defined.
create_clock
It mainly defines the source end of a Clock, the period, the duty cycle (the ratio of the high level of the clock to the period), and the time points of the rising and falling edges of the signal.
Let's take a look at the simplest example:
This clock is described as an sdc statement:
create_clock -name SYSCLK -period 20
-waveform {0 5} [get_ports2 SCLK]
waveform followed by rising edge and falling edge time
-waveform {time_rise time_falltime_rise time_fall ...}
If -period is not specified, the default waveform is {0, period/2}
create_generated_clock
Generated clocks is another important clock concept
generated clocks is the clock definition taken from the master clock. The master clock refers to the clock generation point specified by the create_clock command, as shown in the figure:
We can describe generated clocks with the following command:
#define master clock
create_clock -name CLKP -period 10
-waveform {0 5} [get_pins UPLL0/CLKOUT]
#Define generated clock at point Q
create_generated_clock -name CLKPDIV2
-source UPLL0/CLKOUT
-master_clock CLKP -divide_by 2 [get_pins UFF0/Q]
Generally, we define the source of the clock as create_clock , and the divided clock will be defined as create_generated_clock . The main difference between the two is the CTS step, the generated clock does not generate a new clock domain, and after defining the generated clock, the clock path The starting point is always at the master clock, so that source latency is not recalculated. This is the advantage of defining a generated clock.
Virtual clock
There is also a frequently used concept here is Virtual Clock, virtual clock.
The create_clock and create_generated_clock introduced earlier are real clocks. The virtual clock is not hung on any port or pin, it is just a virtual clock created. As follows:
#define virtual clock
create_clock -name VCLK -period 10 -waveform {0 5}
We usually hang the input/output delay on the virtual clock, because the input/output delay constraint originally refers to the off-chip clock, so it is more reasonable to hang on the virtual clock. Of course, if you want to save things, you can directly hang it on the real clock.
set_clock_uncertainty
It mainly defines the early or late arrival time of the Clock signal to the Clock terminal of the sequential device. Mainly used to reduce the impact of jitter on the effective clock cycle. It is worth noting that in the setup check, the clock uncertainty represents the reduction of the effective period of the clock; in the hold check, the clock uncertainty represents the additional margin that the hold check needs to meet.
Take a look at the following reg2reg path. Compare with the following clock waveform. The following constraints can be written.
set_clock_uncertainty-from VIRTUAL_SYS_CLK
-to SYS_CLK -hold 0.05
set_clock_uncertainty -from VIRTUAL_SYS_CLK
-to SYS_CLK -setup 0.3
set_clock_uncertainty -from SYS_CLK
-to CFG_CLK -hold 0.05
set_clock_uncertainty -from SYS_CLK
-to CFG_CLK -setup 0.1
set_clock_groups
After defining the clock, we also need to confirm the relationship between the clocks by setting the clock group. This is an important step, because usually we also need to do cross domain check. If the clock group is set incorrectly, it will cause the entire STA to check incorrectly. There are generally three options: asynchronous, physically_exclusive and logically_exclusive.
asynchronous represents two asynchronous clock groups
physically_exclusive means that two clock groups are mutually exclusive in a physical sense, for example, two clocks are defined on a source pin.
logically_exclusive means that the two clock groups are logically mutually exclusive, for example, the two clocks pass through the MUX selector. A simple example:
set_clock_groups -physically_exclusive
-group {CLK1 CLK2} -group {CLK3 CLK4}
The definition of clock group is very cautious and needs to be confirmed with the front end again and again.