(1) clock
Q1.1 What is a synchronous clock?
The clock frequency is an integer multiple, and the phase between them is fixed and the difference is predictable, so it can be called a synchronous clock. Everything else is an asynchronous clock.
For example,
5M, 10M are synchronous
2M, 3M is generally asynchronous.
A clock is output to another chip, and after one turn, it returns to its own chip at the same frequency, because the latency of the clock in the other chip cannot be determined. So the output clock is asynchronous with the input clock. If
a clock enters 2 PLLs, even if the output frequencies of the 2 PLLs are the same, they are generally regarded as asynchronous clocks, unless you de-skew
Q1.2 How to deal with synchronous clocks?
For companies with strict design requirements, even if it is a synchronous clock, meta-stability FF is still used when data is transmitted between synchronous clocks. You can set_false_path
if the requirements are relaxed and meta-stability FF is not used, then the real path between synchronous clocks is used for CTS. When synchronizing the clock, the clock tree balance is required.
Note that the minimum time interval of synchronous clocks of different frequencies is used to check the setup
. If the rising and falling edges are mixed, the setup time interval is only half a clock cycle.
Q1.3 How to deal with asynchronous clocks?
Very simple, set_false_path
pay attention to from A to B, and from B to A
Q1.4 How to define the clock?
create_clock If a pin/port is specified, it is a real-time clock. If no pin and port are specified, it is a virtual clock.
Clever use of the waveform option can make clocks with different waveforms. The net
is defined as a clock, and it automatically has the attributes of ideal network and dont_touch during synthesis. But when it is used as data to calculate delay, the property of idealnet disappears automatically set_drive
0 clk
Note:
Toprevent buffering of the clock network, the script sets the input driveresistance of the clock port (clk) to 0 (infinite drive strength).
The clock will automatically pass through the logic unit and stop at the clock end of the sequential unit, so the frequency-divided clock generated by FF needs to be defined again
with create_generated_clock. Q1.5 How to deal with selecting one more clock?
In practical applications, if these clocks do not appear at the same time, when defining the clocks, only the fastest frequency can be selected.
If multiple clocks appear at the same time, you can use set_case_analysis to select one,
or you can put them all In the past, but after the MUX, set_false_path
Q1.6 cleverly defined the clock between them. When defining the generatedclock
directly at the Q end of the frequency division FF, sometimes the timing of the frequency division FF will be destroyed. The solution is to divide the frequency. FF's Q end Add a clock buf, and define the generatedclock from the output of that buf, so as to ensure that the timing of the frequency division FF itself is complete
If there are multiple paths from source clock to generated clock, and you want PT to use a specified path to calculate timing, you can use set_case_analysis, set_disbale_timing or define generated clock level by level to guide PT to meet your
requirements Frequency division The problem of timing constraints of the device
http://bbs.eetop.cn/thread-316442-1-1.html
The problem of different paths of the same clock in timing analysis
Question :
Answer:
First of all, this has nothing to do with CPPR, CPPR compensation is based on the clock of the same path As a premise, ABD and ACD paths are different, so it does not involve CPPR
and then divides it into two cases when doing timing check. Set case analysis is at point D, and ABD and ACD are checked separately.
This is a typical Clockreconvergency problem, the clock source is the same, Then take different paths, and then reconverge on a certain mux. When doing timingcheck, these two paths check each other, and a violation occurs. However, such a path is false, because a mux cannot pass two clocks at the same time.
Solution The method can set case_analysis on mux, each mode only has one path, so the mode will increase, and MMMC needs to be used to solve it. When making a clock tree, the two paths are generally balanced, but there are also cases where they cannot be balanced. , such as DLL.
General solution: If you don't want to use MMMC, define generated_clock at B and C respectively, and then set them both to set_false_path
Q1.7 When do you need to set latency?
There are two types of latency: source latency and network latency. Source latency is provided by the source clock, and networklatency is the clock tree insertion delay after CTS.
During synthesis, latency is generally not required,
unless it
is known that different clocks have different source latency, and there are timing requirements between them. It is
predicted that different clocks will have different clock tree insertion delays. I don't want to balance them, but we must meet their requirements. Timing requirements between
time After completing CTS, remove the network latency
. What’s wrong with setting set_clock_latency too large?
Q1.8 How to set uncertainty
clock uncertainty is divided into setup and hold, preCTS and postCTS in several different situations. The
general processing principle is :
preCTS, setup: uncertainty = PLL jitter + estimated clock skew
preCTS, hold: uncertainty = estimated clock skew
postCTS, set_propagate_clock [all_clocks]
postCTS, setup: uncertainty = PLL jitter
postCTS, hold: uncertainty = 0
Sometimes fundry requires hold uncertainty to reserve a certain amount, then add that reserve amount to
the settings of uncertainty, transition, and latency of clk in the sdc file in the above formula
(2) IO port constraints
Q2.1 How to add IO ports constraints?
The most common method is
for the input, set_input_delay, set_driving_cell (set_input_transition is also useful, but it is rare)
for the output, set_output_delay, set_load
for the clock, set_clock_transition
What setting should the clock transition refer to during dc synthesis?
This is related to the process and design. It is generally recommended that at
65nm, min (1/10 clock cycle, 150ps)
at 90nm, the latter number is 200ps, and 130nm is larger.
However if your clock is particularly slow, it can be smaller. .
set_drive
, set_load The value of set_load and set_drive in the 180nm process dc synthesis is constrained by what reference, there is no concept at all, please help. . . . . .
Answer:
If you know how to place and route,
just assign a value, complete the synthesis, and then do
the backend Get an accurate value from the backend, return to determine the driver and load, and then do the synthesis again
Moderator answer:
set_drive is rarely used
Generally, set_driving_cell.set_load is used to constrain the output port, and set_driving_cell
/set_input_transition is used to constrain the input port
for pad output. The load is generally 10~30pf (large), and
for module output, the load is generally 0.XXX pf
for input transition, Generally larger than a lookup table
How to "set drive" and "set load" in DC?
if this is a digital block inside an analog module, you can request to the analogdesigner, the load/drive capability for each pins and define betterconstraints.
If you want to add this constraint at padlevel, you need to know the PCB used, and every think like this, package....
Ingeneral, I only apply the set load/drive only for pin between analog/digital, because, this could have an impact on timing. The pad are so "slow",this constraints do not add much info.
Q2.2 Which ports do not need constraints?
Static signals can be set_false_path, such as reset, test_mode, function_mode_select
can not really add any constraints.
Q2.3 What kind of reset signal can set_false_path?
If the clock signal does not flip when the reset signal is active during work, you can set_false_path.
If the clock is also active when the reset signal is active, you cannot set_false_path
Q2.4 Do high fanout signals like reset need to be set to ideal net?
If it is a false path, it can be set to ideal net
. Generally, ideal net does not need to be set. After adding DC to the buffer tree, it is beneficial to estimate power consumption and area
Q2.5 If there is a set of output signals, they need to be aligned, but not I care too much about the delay, how should I limit it?
If there is an output clock, define a generated_clock on that output clock port, and the output_delay of other signals is relative to this generated_clock. As long as there are max and min, all signals can be stuck within a range.
If there is no output clock, use set_output_delay -reference_pin
Q2.6 How to calculate input and output delay?
If it is the input and output delay of the block, it can be pre-assigned, such as the output end, the input end is 1/3 each, and the ports connected to the 1/3
block in the middle are preferably flop-in and flop-out.
If it is chip IO, to measure the IO timing of other chips and the delay on the circuit board, it is more troublesome
to set the time of
set_input_delay. Set_input_delay/output_delay is to set the external delay, so as to retain the internal IO delay of the chip to constrain
input io to flop and flop to flop The delay of the output port is
generally constrained to leave 70% outside and 30% inside, but in fact some ports need to be adjusted, not every port needs the same value,
set_input_delay [expr 0.7* $clk_period ] -clock $clk [ all_inputs]
set_output_delay [expr 0.7 * $clk_period ] -clock $clk [all_outputs ]
(3) DRV
DRV is sometimes added with DRC, which is not a concept with the DRC of physical detection.
DRV includes
set_max_transition related to the process, if it is 65nm, it is about 0.6ns
set_max_fanout is related to the process, generally between 12 and 20
set_max_capacitance
set_max_power
set_max_area
4) falsepath, multicycle path
Q4.1 Under what circumstances do you need set_false_path?
between asynchronous clocks,
The first FF path to meta-stability,
static signal
Q4.2 When will multicycle_path be used?
If the path is too long,
the signal will not change every cycle.
Note : In RTL, the front end must work once in multiple cycles.
Generally, set_multicycle_path -setup <n cycles>
write set_multicycle_path -hold <n-1 cycles> at the same time
( 5) wire
load model The wire load model is a method of simply estimating the wire delay according to the fanout. During synthesis, the corresponding WLM is generally selected according to the size of the design.
Sometimes the zero wire load model is also used. At this time, the clock period should be corresponding Decrease 15-25%, or increase clock uncertainty by 15-25%
. What is the difference between top and closed in set_wire_load_model?
The more accurate way to calculate the wire delay is DC topo and RC physical,
they will roughly make a place during synthesis, and then calculate the delay according to the distance
(6) clock gating
Q6.1 How to add clock gating?
Local clock gating will be added automatically during synthesis. After adding clockgating, it will not only reduce power consumption, but also improve timing, because part of the logic that originally went to the D end has been moved to the CK end, which simplifies the logic of the D end
The clock gating of the entire block is generally added directly in the RTL, because DC is not so smart
. Q6.2 Do I need to add any special constraints to the clock gating?
If you use the ICG unit in the standard library, you don't need to attach any special constraints, and the tools at the front and back ends recognize it.
If you use the clock gating built by latch+and, you need to set_disable_clock_gating_check for the and unit, and also tell the back end, be sure to set Latch and and are placed together.
Generally , an and/or can be used for clockgating only when the clock is not dynamically switched. At this time, set_disable_clock_gating_check
(7) case_analysis
set_case_analysis can force a node to be 0/1
. This 0/1 will edge The pure logic combination unit is transmitted forward. If there is no special setting, it will stop at the sequential unit.
Note that it is only forwarded, not left and right and backward.
Example:
If it is set on the output end, then all The fanin terminal will be forced to 0/1
if it is only set on a certain input terminal, the output terminal connected to it and other input terminals will not be affected
(8) ideal net/network
ideal_net only acts on this net
ideal_network will This attribute is transmitted to
clock net automatically with ideal net attribute. When do
other nets need to set ideal net? See Q2.4
Q1.1 What is a synchronous clock?
The clock frequency is an integer multiple, and the phase between them is fixed and the difference is predictable, so it can be called a synchronous clock. Everything else is an asynchronous clock.
For example,
5M, 10M are synchronous
2M, 3M is generally asynchronous.
A clock is output to another chip, and after one turn, it returns to its own chip at the same frequency, because the latency of the clock in the other chip cannot be determined. So the output clock is asynchronous with the input clock. If
a clock enters 2 PLLs, even if the output frequencies of the 2 PLLs are the same, they are generally regarded as asynchronous clocks, unless you de-skew
Q1.2 How to deal with synchronous clocks?
For companies with strict design requirements, even if it is a synchronous clock, meta-stability FF is still used when data is transmitted between synchronous clocks. You can set_false_path
if the requirements are relaxed and meta-stability FF is not used, then the real path between synchronous clocks is used for CTS. When synchronizing the clock, the clock tree balance is required.
Note that the minimum time interval of synchronous clocks of different frequencies is used to check the setup
. If the rising and falling edges are mixed, the setup time interval is only half a clock cycle.
Q1.3 How to deal with asynchronous clocks?
Very simple, set_false_path
pay attention to from A to B, and from B to A
Q1.4 How to define the clock?
create_clock If a pin/port is specified, it is a real-time clock. If no pin and port are specified, it is a virtual clock.
Clever use of the waveform option can make clocks with different waveforms. The net
is defined as a clock, and it automatically has the attributes of ideal network and dont_touch during synthesis. But when it is used as data to calculate delay, the property of idealnet disappears automatically set_drive
0 clk
Note:
Toprevent buffering of the clock network, the script sets the input driveresistance of the clock port (clk) to 0 (infinite drive strength).
The clock will automatically pass through the logic unit and stop at the clock end of the sequential unit, so the frequency-divided clock generated by FF needs to be defined again
with create_generated_clock. Q1.5 How to deal with selecting one more clock?
In practical applications, if these clocks do not appear at the same time, when defining the clocks, only the fastest frequency can be selected.
If multiple clocks appear at the same time, you can use set_case_analysis to select one,
or you can put them all In the past, but after the MUX, set_false_path
Q1.6 cleverly defined the clock between them. When defining the generatedclock
directly at the Q end of the frequency division FF, sometimes the timing of the frequency division FF will be destroyed. The solution is to divide the frequency. FF's Q end Add a clock buf, and define the generatedclock from the output of that buf, so as to ensure that the timing of the frequency division FF itself is complete
If there are multiple paths from source clock to generated clock, and you want PT to use a specified path to calculate timing, you can use set_case_analysis, set_disbale_timing or define generated clock level by level to guide PT to meet your
requirements Frequency division The problem of timing constraints of the device
http://bbs.eetop.cn/thread-316442-1-1.html
The problem of different paths of the same clock in timing analysis
Question :
Answer:
First of all, this has nothing to do with CPPR, CPPR compensation is based on the clock of the same path As a premise, ABD and ACD paths are different, so it does not involve CPPR
and then divides it into two cases when doing timing check. Set case analysis is at point D, and ABD and ACD are checked separately.
This is a typical Clockreconvergency problem, the clock source is the same, Then take different paths, and then reconverge on a certain mux. When doing timingcheck, these two paths check each other, and a violation occurs. However, such a path is false, because a mux cannot pass two clocks at the same time.
Solution The method can set case_analysis on mux, each mode only has one path, so the mode will increase, and MMMC needs to be used to solve it. When making a clock tree, the two paths are generally balanced, but there are also cases where they cannot be balanced. , such as DLL.
General solution: If you don't want to use MMMC, define generated_clock at B and C respectively, and then set them both to set_false_path
Q1.7 When do you need to set latency?
There are two types of latency: source latency and network latency. Source latency is provided by the source clock, and networklatency is the clock tree insertion delay after CTS.
During synthesis, latency is generally not required,
unless it
is known that different clocks have different source latency, and there are timing requirements between them. It is
predicted that different clocks will have different clock tree insertion delays. I don't want to balance them, but we must meet their requirements. Timing requirements between
time After completing CTS, remove the network latency
. What’s wrong with setting set_clock_latency too large?
Q1.8 How to set uncertainty
clock uncertainty is divided into setup and hold, preCTS and postCTS in several different situations. The
general processing principle is :
preCTS, setup: uncertainty = PLL jitter + estimated clock skew
preCTS, hold: uncertainty = estimated clock skew
postCTS, set_propagate_clock [all_clocks]
postCTS, setup: uncertainty = PLL jitter
postCTS, hold: uncertainty = 0
Sometimes fundry requires hold uncertainty to reserve a certain amount, then add that reserve amount to
the settings of uncertainty, transition, and latency of clk in the sdc file in the above formula
(2) IO port constraints
Q2.1 How to add IO ports constraints?
The most common method is
for the input, set_input_delay, set_driving_cell (set_input_transition is also useful, but it is rare)
for the output, set_output_delay, set_load
for the clock, set_clock_transition
What setting should the clock transition refer to during dc synthesis?
This is related to the process and design. It is generally recommended that at
65nm, min (1/10 clock cycle, 150ps)
at 90nm, the latter number is 200ps, and 130nm is larger.
However if your clock is particularly slow, it can be smaller. .
set_drive
, set_load The value of set_load and set_drive in the 180nm process dc synthesis is constrained by what reference, there is no concept at all, please help. . . . . .
Answer:
If you know how to place and route,
just assign a value, complete the synthesis, and then do
the backend Get an accurate value from the backend, return to determine the driver and load, and then do the synthesis again
Moderator answer:
set_drive is rarely used
Generally, set_driving_cell.set_load is used to constrain the output port, and set_driving_cell
/set_input_transition is used to constrain the input port
for pad output. The load is generally 10~30pf (large), and
for module output, the load is generally 0.XXX pf
for input transition, Generally larger than a lookup table
How to "set drive" and "set load" in DC?
if this is a digital block inside an analog module, you can request to the analogdesigner, the load/drive capability for each pins and define betterconstraints.
If you want to add this constraint at padlevel, you need to know the PCB used, and every think like this, package....
Ingeneral, I only apply the set load/drive only for pin between analog/digital, because, this could have an impact on timing. The pad are so "slow",this constraints do not add much info.
Q2.2 Which ports do not need constraints?
Static signals can be set_false_path, such as reset, test_mode, function_mode_select
can not really add any constraints.
Q2.3 What kind of reset signal can set_false_path?
If the clock signal does not flip when the reset signal is active during work, you can set_false_path.
If the clock is also active when the reset signal is active, you cannot set_false_path
Q2.4 Do high fanout signals like reset need to be set to ideal net?
If it is a false path, it can be set to ideal net
. Generally, ideal net does not need to be set. After adding DC to the buffer tree, it is beneficial to estimate power consumption and area
Q2.5 If there is a set of output signals, they need to be aligned, but not I care too much about the delay, how should I limit it?
If there is an output clock, define a generated_clock on that output clock port, and the output_delay of other signals is relative to this generated_clock. As long as there are max and min, all signals can be stuck within a range.
If there is no output clock, use set_output_delay -reference_pin
Q2.6 How to calculate input and output delay?
If it is the input and output delay of the block, it can be pre-assigned, such as the output end, the input end is 1/3 each, and the ports connected to the 1/3
block in the middle are preferably flop-in and flop-out.
If it is chip IO, to measure the IO timing of other chips and the delay on the circuit board, it is more troublesome
to set the time of
set_input_delay. Set_input_delay/output_delay is to set the external delay, so as to retain the internal IO delay of the chip to constrain
input io to flop and flop to flop The delay of the output port is
generally constrained to leave 70% outside and 30% inside, but in fact some ports need to be adjusted, not every port needs the same value,
set_input_delay [expr 0.7* $clk_period ] -clock $clk [ all_inputs]
set_output_delay [expr 0.7 * $clk_period ] -clock $clk [all_outputs ]
(3) DRV
DRV is sometimes added with DRC, which is not a concept with the DRC of physical detection.
DRV includes
set_max_transition related to the process, if it is 65nm, it is about 0.6ns
set_max_fanout is related to the process, generally between 12 and 20
set_max_capacitance
set_max_power
set_max_area
4) falsepath, multicycle path
Q4.1 Under what circumstances do you need set_false_path?
between asynchronous clocks,
The first FF path to meta-stability,
static signal
Q4.2 When will multicycle_path be used?
If the path is too long,
the signal will not change every cycle.
Note : In RTL, the front end must work once in multiple cycles.
Generally, set_multicycle_path -setup <n cycles>
write set_multicycle_path -hold <n-1 cycles> at the same time
( 5) wire
load model The wire load model is a method of simply estimating the wire delay according to the fanout. During synthesis, the corresponding WLM is generally selected according to the size of the design.
Sometimes the zero wire load model is also used. At this time, the clock period should be corresponding Decrease 15-25%, or increase clock uncertainty by 15-25%
. What is the difference between top and closed in set_wire_load_model?
The more accurate way to calculate the wire delay is DC topo and RC physical,
they will roughly make a place during synthesis, and then calculate the delay according to the distance
(6) clock gating
Q6.1 How to add clock gating?
Local clock gating will be added automatically during synthesis. After adding clockgating, it will not only reduce power consumption, but also improve timing, because part of the logic that originally went to the D end has been moved to the CK end, which simplifies the logic of the D end
The clock gating of the entire block is generally added directly in the RTL, because DC is not so smart
. Q6.2 Do I need to add any special constraints to the clock gating?
If you use the ICG unit in the standard library, you don't need to attach any special constraints, and the tools at the front and back ends recognize it.
If you use the clock gating built by latch+and, you need to set_disable_clock_gating_check for the and unit, and also tell the back end, be sure to set Latch and and are placed together.
Generally , an and/or can be used for clockgating only when the clock is not dynamically switched. At this time, set_disable_clock_gating_check
(7) case_analysis
set_case_analysis can force a node to be 0/1
. This 0/1 will edge The pure logic combination unit is transmitted forward. If there is no special setting, it will stop at the sequential unit.
Note that it is only forwarded, not left and right and backward.
Example:
If it is set on the output end, then all The fanin terminal will be forced to 0/1
if it is only set on a certain input terminal, the output terminal connected to it and other input terminals will not be affected
(8) ideal net/network
ideal_net only acts on this net
ideal_network will This attribute is transmitted to
clock net automatically with ideal net attribute. When do
other nets need to set ideal net? See Q2.4