A Synchronized Asynchronous Reset Circuit Design in FPGA

The design comes from "FPGA Design Practical Exercises (Advanced Skills)"

 

Take advantage of synchronous reset and asynchronous reset, avoid their disadvantages. A synchronous asynchronous reset circuit is designed, the advantages and disadvantages of synchronous reset and asynchronous reset are given, and the schematic diagram and verilog code are given.

 

1. Synchronous reset

Advantages: easy timing analysis and simulation

Disadvantages: The pulse width of the reset signal is required to meet certain requirements to ensure that the reset clock edge reset signal is valid, which is slower than asynchronous reset

 

2. Asynchronous reset

Advantages: There is an asynchronous reset port on the logic resource, and the resource can be fully utilized. fast response

Disadvantages: sensitive to noise, there is a metastable problem,

 

3. Asynchronous reset synchronization

The asynchronous reset is directly connected to the CLR port of the register, so that the reset takes effect immediately. When the reset is removed, a logic "1" is clocked out from the synchronizer to release the reset of subsequent registers synchronously, so in this structure, the asynchronous reset of the design is removed synchronously,

module reset(
input clock,
input reset_n,
input data_a,
input data_b,
output out_a,
output out_b
    );
    
reg reg1,reg2;
reg reg3,reg4;
wire rst_n;

assign out_a = reg1;
assign out_b = reg2;
assign rst_n = reg4;

always@(posedge clock or negedge reset_n)
begin
    if(!reset_n)
    begin
        reg3 <= 1'b0;
        reg4 <= 1'b0;
    end
    
    else
    begin
        reg3 <= 1'b1;
        reg4 <= reg3;
    end
end

always@(posedge clock or negedge rst_n)
begin
    if(rst_n)
    begin
        reg1 <= 1'b0;
        reg2 <= 1'b0;
    end
    else
    begin
        reg1 <= data_a;
        reg2 <= data_b;
    end
end
endmodule