[Verilog] Asynchronous reset and synchronous reset Comparison
|
|
Synchronous reset sync |
Asynchronous reset async |
| Feature |
Reset signal is only valid when the clock rising edge. |
Regardless of whether the clock edge arrival, as long as the reset signal is active, it is reset. |
| Verilog description |
always@(posedge CLK) |
always@(posedge CLK , negedge Rst_n) |
| advantage |
1) favor simulator simulation. 2) Because only valid when the clock active level soon, so you can filter out the higher clock frequency glitches. 3) The system can be designed so that 100% of the synchronous sequential circuit, facilitate timing analysis. |
1) design is relatively simple. 2) Because the majority of the target device dff library has asynchronous reset port, so using asynchronous reset can save resources. 3) facilitate the identification signal asynchronous reset, and can easily use the global reset port GSR FPGA. |
| Shortcoming |
1) when the effective length of the reset signal must be greater than the clock cycle, and can actually recognized by the system reset is complete the task. Also to be considered, such as: clk skew, combinational logic path delay, reset delay and other factors.
2) Since most of the interior of the target logic device are both DFF asynchronous reset port, therefore, if the synchronous reset, it will synthesizer logic composition insertion port data input register, which would consume more logic resources. |
1) reset signal susceptible to the influence of burrs.
2) prone to problems when the reset signal is released (release) of. That is specifically: if the reset release just near the active clock edge, it is easy to register output metastability occurs, leading to metastability. |
| to sum up |
Recommended use asynchronous reset mode, the synchronization is released, and the reset signal is active low. |
|
Related discussion:
1. What is the difference between synchronous and asynchronous circuits are?
Asynchronous circuit is mainly a combinational logic circuit, for generating an address decoder, a read FIFO or RAM control signal pulse, but it is also used in the sequential circuit, it is not uniform at this time clock, the time is not the state change stable, generally the input signal changes only occur when the circuit is in a steady state. That is a time to allow a change in input, in order to avoid competition caused between the signal input adventure. Stabilization circuit requires reliable setup and hold times, to be described below.
Synchronizing circuit is a circuit by the timing circuit (various registers and flip-flops) and a combinational logic circuit, where all operations are performed under strict clock control. These timing circuits share the same clock CLK, and all the changes in state of the clock rising edge (or falling edge) is completed. Such as D flip-flop, when the rising delay the arrival of the register level D Q output terminal of the spread.
In the synchronization circuit generally used D flip-flop, generally use an asynchronous circuit design Latch.
2. What is the logic synchronous and asynchronous logic?
Synchronization logic is a causal relationship between a fixed clock. Asynchronous logic is no causal relationship between the fixed clock.
Circuit design may be classified into synchronous and asynchronous circuits design. Using a clock synchronization circuit subsystems operate synchronously so, the asynchronous circuits do not use synchronized clocks, which subsystem is to use special "start" and "done" signal to make synchronization. Because of the asynchronous circuit has the following advantages - no clock skew problems, low power consumption, rather than average performance worst performance, modularity, reusability may be combined and - so in recent years rapidly increased study of the asynchronous circuit, to multiply the number of papers published , the Intel Pentium 4 processor designs are beginning to use asynchronous circuit design.
Asynchronous circuit is mainly a combinational logic circuit, for generating an address decoder, a read FIFO or RAM control signal pulse, the output logic does not matter any clock signal, the decoder outputs the generated burr can generally be monitored. Synchronizing circuit is a circuit by the timing circuit (various registers and flip-flops) and a combinational logic circuit, where all operations are performed under strict clock control. These timing circuits share the same clock CLK, and all the changes in state of the clock rising edge (or falling edge) is completed.
3. What is the "line" logic to achieve it, and what specific requirements on hardware features?
Line and the output signals are logically connected to two functions can be achieved. In hardware, to implement use oc gate (drain or open collector), because they are not likely to sink oc gate current is too large, burn logic gates, while the output pull-up resistor should be added to a port. (Or wire is pull-down resistor)
4. What is the Setup and Holdup time?
5, setup and holdup time difference.
6, explanation define setup time and hold time and changes when the delayed clock signal.
7, explanation setup and hold timeviolation, drawing illustrate and explain solutions.
Time (Setup Time) and hold time (Hold time). Before the setup time refers to the clock edge, data signal needs to be constant in time. Retention time refers to the clock edge transition signal after the data needs to be constant in time. If not setup and hold times, then DFF will not be properly sampled data, the situation metastability will appear. If the data signal duration in excess of setup and hold times before and after the clock edge trigger, then it is more than the amount called setup time margin and the hold time margin.
8, talk about the understanding of the digital logic of competition and adventure, and examples of how to eliminate competition and adventure.
9. What is the phenomenon of competition and adventure? How do we judge? How to eliminate?
In combinatorial logic in the input signal path of the door after a different delay, leading to inconsistency of the door arrival time called competition. Called burrs adventure. If you have the opposite signal Boolean equation may produce the phenomenon of competition and adventure. Solution: First, add Bramble-esque (redundant) eliminate items, but can not avoid risky features, plus the second is external capacitor chip. Third, increasing gate circuit
In combinatorial logic, since the input signal changes has a different number, different signal transmission paths, or a variety of different time delay device (a phenomenon known as competitive) may have resulted in the output waveform undue spikes (known as burr), this phenomenon has become risky.
10, you know what common logic level? TTL and COMS level can directly interconnect it?
Common logic levels: TTL, CMOS, LVTTL, LVCMOS , ECL (Emitter Coupled Logic), PECL (Pseudo / PositiveEmitter Coupled Logic), LVDS (Low Voltage Differential Signaling), GTL (GunningTransceiver Logic), BTL (Backplane Transceiver Logic), ETL (enhancedtransceiver logic), GTLP ( Gunning Transceiver Logic Plus); RS232, RS422, RS485 (12V, 5V, 3.3V); TTL and CMOS can not be directly interconnected, since the TTL is between 0.3-3.6V, and CMOS there is at 5V to 12V there is. CMOS TTL output can be connected directly interconnected. TTL to CMOS requires 12V to 5V at the output port or add a pull-up resistor.
cmos high and low, respectively: V ih> = 0.7VDD, Vil <= 0.3VDD; Voh> = 0.9VDD, Vol. <= 0.1VDD.
TTL is: Vih> = 2.0v, Vil < = 0.8v; Voh> = 2.4v, Vol <= 0.4v.
with direct drive TTL cmos; plus the pull-up resistor, can drive TTL cmos.
. 1, when the TTL circuit COMS driving circuit, if the circuit output is less than the high level TTL circuit COMS minimum high level (typically 3. 5V), then you need to pull TTL output termination resistors to improve the output of high value.
2, OC gate pull-up resistor must be added, to increase the level value out output.
3, to increase the driving capacity of the output pins, some MCU pins often pull-up resistors.
4, in the COMS chip, in order to prevent damage from static electricity, can not be suspended without pins, generally produce decreased pull-up resistor input impedance, providing unloading passage.
5, pins of the chip pull-up resistor to raise the output level, thereby improving the noise margin of an input signal enhancement chip interference.
6, improve anti-electromagnetic interference capability to the bus. Pin is floating is more receptive to external electromagnetic interference.
7, long transmission prone to resistor mismatch reflected wave interference, plus the pull-down resistor is a resistance matching, effectively suppressing reflection wave interference.
Pullup resistor selection principle include:
1, the sink current capability and power saving considerations should be sufficiently large chip; large resistance, current is small.
2, ensuring a sufficient drive current should be small enough to consider; low resistance, large current.
3, a circuit for high-speed, large pull-up resistor may be flattened edge. Considering the
above three points, usually choose between 1k to 10k. Pull-down resistors have a similar reason
// OC gate pull-up resistor must be added, to increase the value of the output level out.
OC to gate circuit outputs "1" when the pull-up resistor without need simply not high
we sometimes used as a driving OC gate (e.g., a control LED) can not sink current when the pull-up resistor work
OC gate can have a "line" operation
OC open collector output gate is
short pull-up resistor can be improved drive capability.
11, how to solve the metastable state. ?
Metastable state are triggers that can not be specified in a certain period of time to achieve a recognized state. When a flip-flop goes metastable, both can not predict the output level of the unit can not predict when the output can be stabilized at a proper level. In this stable period, the flip-flop outputs some intermediate stage level, or may be in an oscillation state, and such a useless output level can propagate down along the cascaded flip-flops on the signal path.
Solution:
1 to reduce system clock frequency
2 with faster reaction FF
3 synchronization mechanism is introduced, to prevent the propagation of metastable
4 to improve the clock quality, fast clock signal edge change of
the key processes and devices use better clock cycles margin larger. Metastable register with d just one way, sometimes by not, buf, etc. to achieve signal filtering effect
12, IC design difference between the simultaneous resetting the asynchronous reset.
Synchronous reset clock edge mining reset signal, the reset operation is completed. Regardless of clock asynchronous reset, the reset signal as long as the condition is satisfied, the reset operation is completed. Asynchronous reset of the reset signal is relatively high, we can not have glitches, not sure if its relationship with the clock, it may appear metastable state.
13 wherein, MOORE and MEELEY state machine.
Moore state machine output only the values related to the current state, and only when there is a state change in the arrival of the clock edge. Mealy state machine output not only related to the current state value, and the value relating to the input current, this
14, a long time domain design how to handle signals across the time domain.
Between different clock domains require communication sync signal, a signal which prevents metastable first flip new clock domain affect subordinate logic, wherein the control signal may be for a single two-stage synchronizer, such as level, and a pulse edge detection, the FIFO may be multi-bit signals, dual-port RAM, the handshake signals.
Across the time domain signal through the synchronizer to synchronize metastable prevent propagation. For example: a signal in clock domain 1, to be sent to the clock domain 2, then the signal is supplied before the clock domain 2, after the first clock domain synchronous synchronizer 2, 2 clock domain to enter. The synchronizer flip-flop d is two, clock 2 clock domain clock. This is afraid that the signal clock domains 1, 2 may not meet the established trigger clock domains hold time, to produce metastable, because there is no necessary relationship between them, are asynchronous. Doing so only to prevent the spread of the metastable state, but can not guarantee the correctness of the incoming data mining. It is usually only a small number of bits of the synchronization signal. Such as control signals or address. When the synchronization is to address, this address should be generally Gray code as a time code becomes a Gray, equivalent to only one synchronizer function, which can reduce the error probability, like asynchronous FIFO design, comparing the size of the read address is to use this method. If a large amount of data transfer between the two clock domains, asynchronous FIFO can be used to solve the problem.
We can add a low level so that LockupLatch energy when crossing Clock Domain to ensure Timing can correct.
Verilog in the asynchronous reset and synchronous reset (rpm)
1. The synchronous reset (SynchronousReset)
A simple look at the synchronous reset of the D flip-flop, Verilog code as follows:
module d_ff
(clk, rst_n, datain,>
else
dataout <= datain;
end
endmodule
Synchronous reset advantages:
1) high anti-interference, it can eliminate the reset period is shorter than the signal glitch clock cycle;
2) in favor of static timing analysis tools;
3) simulation cycle-based simulation tools in favor.
Synchronous reset Disadvantages:
1) consume more logic resources;
. 2) has a pulse width of the reset signal is required to be larger than the specified clock cycle, due to the delay on the line, the pulse width may need to reset the plurality of clock cycles, and it is difficult to ensure the timing of the reset signal reaches the respective register;
3) Synchronous reset is dependent on the clock, the clock signal circuit if there is a problem, not the reset is completed.
2. Asynchronous Reset (Asynchronous Reset)
Examine a simple asynchronous reset D flip-flops, Verilog code as follows:
module prac ( clk, rst_n, datain, dataout );
input clk;
input rst_n;
input datain;
output dataout;
reg dataout;
always @(posedge clk
else
dataout <= datain;
end
endmodule
Asynchronous reset advantages:
1) No additional logic resources, simple, CPLD and there is a global reset signal for the limited resources, can guarantee the reset pin of each register to the minimum clock skew (note not to register the respective minimum delay);
2) The reset signal does not depend on a clock.
Synchronous reset Disadvantages:
1) a reset signal susceptible to outside interference;
2). Randomness releasing the reset signal, may result in timing violations, so that the circuit is metastability, as shown below.
3. synchronous asynchronous reset release (Asynchronous Reset Synchronous Release)
This reset method in the literature there is a title: SynchronizedAsynchronous Reset, this title should be more popular in foreign technical staff, engineers and Altera communication process in which they have been using Synchronized AsynchronousReset this title (of course, may be personal habit).
A look SynchronizedAsynchronous Reset example, Verilog code as follows:
module prac ( clk, reset_n, dataa, datab, outa, outb );
input clk;
input reset_n;
input dataa;
input datab;
output outa;
output outb;
reg reg1;
reg reg2;
reg reg3;
reg reg4;
assign outa => assign rst_n = reg4;
always @(posedge> reg4 <= 1’b0;
end
else
begin
reg3 <= 1’b1;
reg4 <= reg3;
end
end
always @ (posedge> reg2 <= 1’b0;
end
else
begin
reg1 <=> end
end
endmoduleRTL chart after summarized as follows:
Article from "Implementationand Timing of Reset Circuits in Altera FPGAs", examples of the program code may be slightly different from the source code, the RTL FIG QuartusII 8.1 is integrated, and also differ from the original.
Asynchronous reset, synchronous release
FPGA design common Reset i.e. synchronous reset and asynchronous reset. After Before exploring the metastable this concept, many people do not have too much attention to reset so-called synchronous and asynchronous reset, but in practice to fully experience the metastable harm come back to savor "Verilog HDL design and verification, "a book chapter on reset, can be described as benefit.
Mostly used in the previous code is asynchronous reset.
A simple example of asynchronous reset
always @ (posedge clk or negedgerst_n)
if(!rst_n)b <= 1’b0;
elseb <= a;
We can see FPGA registers has a asynchronous clear terminal (CLR), in the design of this asynchronous reset port is generally connected to an active low reset signal rst_n. Even if say your design is reset high, then the actual overall will reverse after you reset signal CLR to take up this end.
A simple example of synchronous reset
always @ (posedge clk)
if(!rst_n)b <= 1’b0;
elseb <= a;
And compared with asynchronous reset, synchronous reset register CLR no access port, just out of the actual integrated circuit reset signal rst_n as a logic enable signal input. So, this synchronous reset is bound to consume additional resources inside the FPGA.
So synchronous reset and asynchronous reset in the end it is better?
I can only say, advantages and disadvantages. Synchronous reset is good that it only triggers on the rising edge of the clock signal clk to determine whether a system reset, which reduces the probability of occurrence of metastable; it's not said above, is that it requires more device resources , which we do not want to see. FPGA registers have a dedicated port supports asynchronous reset, using the port without additional consumption of resources of asynchronous reset of the device, but there are also risks asynchronous reset, privileged students from the past do not realize nor seen. Metastability asynchronous clock domains between the presence of the same asynchronous reset signal and a system clock signal.
Look at the following example of a two asynchronous reset register
always @ (posedge clk or negedgerst_n)
if(!rst_n)b <= 1’b0;
elseb <= a;
always @ (posedge clk or negedgerst_n)
if(!rst_n)c <= 1’b0;
elsec <= b;
Under normal circumstances, clk rising edge c is updated to b, b to update a. Once inside reset, b, c are cleared; but we can not determine the reset signal rst_n will end at what time. If the ends of b_reg0 and c_reg0 {launch edge -stup, launchedge + hold} only the outer time, everything will be normal. But if the contrary, what happens then? Rst_n upward change occurs in the rising establishment clk holding time, at this time the clk detected rst_n metastable state would be a (0 1 uncertain). If we see from the code at this time b_reg0 and c_reg0 think rst_n is 0, then the reset remains clear, and if deemed rst_n is 1, then jump out reset. Rst_n because the uncertainty of four cases can occur, i.e. b_reg0 and c_reg0 are reset or a reset out of all, and then out of a reset or a reset. Then the latter will cause the system to work without problems synchronizing, in this simple asynchronous reset two examples of such harm is done is not obvious, but we imagine a large number of projects in such a situation would arise register It is how the big picture it?
The above analysis seems to make people aware of the synchronous reset and asynchronous reset is not reliable, then how will a combination of both, learning from it.
Asynchronous reset, synchronous release
always @ (posedge clk)
rst_nr<= rst_n; //现将异步复位信号用同步时钟打一拍
always @ (posedge clk or negedgerst_nr)
if(!rst_nr)b <= 1’b0;
elseb <= a;
always @ (posedge clk or negedgerst_nr)
if(!rst_nr)c <= 1’b0;
elsec <= b;
In this way, not only solve the problem of resource depletion synchronous reset, but also solve the problem of metastable asynchronous reset. The fundamental idea, also asynchronous signal synchronization.
Also privileged students consulted IC Design Department, a senior expert, similar to their usual way in the design and reset the above method, roughly as follows:
Synchronous and asynchronous reset in VHDL and Verilog
Difference between these two ways of resetting mainly to see whether to participate clock: clock asynchronous reset is not required to participate, as long as a valid reset signal on the reset operation is performed immediately; clock synchronization signal required to participate, and only when the clock is valid, the reset signal along to be effective.
The greatest benefit of synchronous reset operation is effective to prevent an erroneous reset signal caused by the glitch reset, as long as the clock is not valid glitch occurs near the edge, it will not affect the normal operation of the circuit; and if the asynchronous reset, the burrs which immediately causes the reset signal reset circuit .
Asynchronous reset can be accomplished at a clock is not reset, it is possible to complete the reset circuit when the power system, and synchronous reset fewer resources than asynchronous reset consumed. In general, as long as can guarantee the stability of the reset signal, we recommend using asynchronous reset.
We look at both synchronous and asynchronous reset in VHDL and Verilog implementation details:
VHDL:
PROCESS (clk, reset) - Reset Synchronization
BEGIN
If(rising_edge(clk)) then
If (reset = '1') then- reset signal is active clock edge is determined at
- the reset operation
End if;
End if;
END
PROCESS (clk, reset) - Asynchronous reset
BEGIN
If (reset = '1') then- reset signal need not be at the active clock edge determination
- the reset operation
elsif(rising_edge(clk)) then
……….
End if;
END
Verilog：
always @ (posedge clk or posedge reset)//异步复位，在敏感信号里加复位信号
if(reset)
begin
//执行复位操作
end
else
begin
……
end
always @ （posedgeclk）//同步复位，在敏感信号不用加复位信号
if(reset)
begin
//执行复位操作
end
else
begin
……
End
Comparison of asynchronous and synchronous reset Reset
Their advantages and disadvantages:
1, in general, the advantages of synchronous reset of about 3:
a, simulation simulator favor.
b, can make the system designed to be 100% of synchronous sequential circuits, which would greatly benefit timing analysis, and comprehensive out fmax is generally higher.
c, because he is only valid when the clock active level soon, so you can filter out the higher clock frequency glitches. He also has many shortcomings, mainly in the following few:
When the effective length a, the reset signal must be greater than the clock cycle, and can actually recognized by the system reset is complete the task. Also to be considered, such as: clk skew, combinational logic path delay, reset delay and other factors.
B, since most of the interior of the target logic device are both DFF asynchronous reset port, therefore, if the synchronous reset, it will synthesizer logic composition insertion port data input register, which would consume more logic resources.
2, for the asynchronous reset, he also has three advantages, are corresponding to
a, dff most libraries target device has asynchronous reset port, and therefore resources can be saved using asynchronous reset.
b, a relatively simple design.
C, asynchronous reset signal to facilitate identification, and can easily use the global reset port GSR FPGA.
Disadvantages:
a, prone to problems when the reset signal is released (release) of. DETAILED say: just in the vicinity of the effective edge of the clock, it is easy for the output register occurs when metastable if a reset release, resulting metastable.
b, a reset signal is easily affected by the burr.
Third, the summary:
So, it is generally recommended to use asynchronous reset, synchronization of the release, and active-low reset signal. This can be the best of both worlds.
Recommended Reset
The so-called reset method is recommended above said: "asynchronous reset, synchronous release." This combines the advantages of both ways, well overcome the shortcomings of asynchronous reset (due to the asynchronous reset of the main problems occur when the reset signal is released, the specific reasons seen above).
In fact, it is not difficult to do, I recommend a way I often use it: that is to add a so-called "reset synchronizer" After asynchronous reset button, so you can make an asynchronous reset signal synchronization, and then, again after the system reset signal to effect treatment, it is possible to ensure a relatively stable. The reset sychronizer Verilog code as follows:
moduleReset_Synchronizer(output reg rst_n, input clk, asyncrst_n);
reg rff1;
always @ (posedge clk ,negedge asyncrst_n) begin
if (!asyncrst_n) {rst_n,rff1}<= 2’b0;
else {rst_n,rff1} <={rff1,1’b1};
end
endmoduleWe can see that this is a DFF, directly connected to asynchronous reset signal at its asynchronous reset port (active low), then the data has been input rff1 high '1'. If the asynchronous reset signal is active, then flip-flop is reset, output is low, thereby resetting the successor systems. However, and as this is the clock edge trigger, when the reset signal is released, the flip-flop output is delayed by one clock cycle to be restored to '1', so that the reset signal is released along with clock synchronization. In addition, there is a more direct method is to add a D flip-flop directly after the asynchronous reset signal, and then output as a reset signal of the D flip-flop after the stage system, can achieve the same effect. There is not much to say.
3: The method of processing multi-clock system reset)
This is a very real problem, because in larger systems, a drive clock signal obviously does not meet requirements, will be homologous with a plurality of clock according to system requirements (of course also be a non-homologous) to the drive system different parts. So in such a multi-clock system, how to set the reset button? Its stability is directly related to the stability of the entire system, so pay special attention to (in my opinion, the status of the reset signal and the clock signal synchronized timing system as important). Here say what specific approach, of course, the principle still followed it should be "asynchronous reset, synchronize the release of" above:
1.non-coordinated resetremoval: As the name suggests, is a system with a plurality of clock domains homologous reset signal, independently of each other by the "reset synchronizer" drive. When the asynchronous reset signal is asserted, each of the simultaneous reset clock domain, but the reset release time determined by the respective driving clock, is said: first clock fast release, slow clock after the release, but there is no relationship between the reset signal has .
2.sequence coordinated resetremoval: This is with respect to the above-described manner is, that each of the reset signals related to each other clock domains, the various parts of the system while also reset, but graded release. Classification is determined by the order of each cascade "reset synchronizer" of. May be reset before class, and then reset level, it may be reversed. Anyway, very flexible, and need to be based on actual needs. Since the image upload problem, I can only express the program, we join in or see, ha ha
Examples: three system reset, system clock, respectively 1M, 2M, 11M:
第一级Reset_Sychronizer程序:
moduleReset_Synchronizer(output reg rst_n, input clk, asyncrst_n);
reg rff1;
always @ (posedge clk , negedge asyncrst_n)
begin
if (!asyncrst_n) {rst_n,rff1}<= 2’b0;
else {rst_n,rff1} <={rff1,1’b1};
end
endmodule
第2，3级的Reset_Sychronizer程序：
moduleReset_Synchronizer2(output reg rst_n, input clk, asyncrst_n,d);
reg rff1;
always @ (posedge clk ,negedge asyncrst_n) begin
if (!asyncrst_n) {rst_n,rff1}<= 2’b0;
else {rst_n,rff1} <={rff1,d};
end
endmodule
顶层模块的源程序：
include”Reset_Synchronizer.v”
include”Reset_Synchronizer2.v”
moduleAsynRstTree_Trans
(input Clk1M,Clk2M,Clk11M,SysRst_n, output SysRst1M_n,SysRst2M_n,SysRst11M_n);
Reset_SynchronizerRst1M(.clk(Clk1M),. asyncrst_n(SysRst_n),.rst_n(SysRst1M_n));
Reset_Synchronizer2Rst2M(.clk(Clk2M),.d(SysRst1M_n),.asyncrst_n(SysRst_n),.rst_n(SysRst2M_n));
Reset_Synchronizer2Rst11M(.clk(Clk11M),.d(SysRst2M_n),. asyncrst_n(SysRst_n),.rst_n(SysRst11M_n));
Endmodule
