Frequency dividing circuit design

table of Contents

1. even-minute 频

2. odd division

3. The half-integer divider

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        Divider is one common design FPGA, it served an important role in FPGA design (clock for FPGA circuitry importance of self-evident!). Although most widely used designs can vendor integrated the PLL frequency division resources, frequency and phase shift (for each vendor Xilinx / Alter et development kit which provides the IP of each), but not ask the clock the basic design still need to design the phase shift divider, phase locked loop can save resources.

        Reference frequency, may be set for a beginner would think of using a counter substrate before the next clock count, the clock obtained by inverting desired. Such a method can be implemented indeed even frequency division, but the implementation odd division, it may not be a counter, generally require two counters.

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1. even-minute 频

      Even frequency division is more common than the odd division, through a counter can be completely realized. The need to divide by N (N is an even number, N / 2 is an integer), it can be recycled in the odd-numbered divided clock to be triggered by a counter. When the counter / odd -1 to N 2 0, and outputs inverted clock.

Verilog implementation:

module even(  
    clk_in    ,
    rst_n     ,
    clk_out   
);

input      clk_in;
input      rst_n;
output reg clk_out;

parameter N=6;   //定义分频参数
reg [3:0] cnt;

always @(posedge clk_in or negedge rst_n)
begin
 if(!rst_n) 
    begin    
       cnt     <= 4'b0000  ;
       clk_out <= 1'b0     ;
    end
 else if(cnt==(N/2-1)) 
    begin
      clk_out <= ~clk_out;
      cnt     <= 4'b0000;
    end 
 else 
    cnt<=cnt+1; 
 end

endmodule

 

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2. odd division

        First look at the division of the timing diagram:

 Can be seen from the timing diagram for odd division, respectively, by the main clock is a rising edge trigger the generation of a clock, and then generates a set of clock falling edge, and the two operation to obtain a clock signal or odd division result.

If N is odd, then N / 2 non-integral of (N-1/2 is an integer), then how to achieve it?

Implementation is:

        Step1 : double counter edge;

                     Using two counters: cnt_up and cnt_down, respectively, and the trigger counter cnt_up cnt_down clock rising edge.

        Step2 : generating two control signals and Clk_up Clk_down;

                    cnt_up counts to (N-1) / 2-1 level inverted signal Clk_up, and then counts to N-1 level signal is inverted Clk_up, while cnt_down counts (N-1) / 2-1 level inverted signal Clk_down, then count to N-1 level of the inverted signal Clk_down.

        Step3 : After obtaining divided clock;

               If Clk_up signal and Clk_down Clk_up Clk_out relationship with high and low level signals Clk_down than about (duty ratio):

               (1) If the high / low ratio of 1-N / 2       : N-1/2 + 1   , the frequency-divided clock clk_div = clk_up || clk_down (Figure 1).

               (2) If the high / low ratio. 1-N / 2  + 1'd: N / 2, the frequency-divided clock clk_div = clk_up && clk_down (Figure 2).

module div3(
     clk     ,
     rst_n   ，
     clk_out 
    );

input     clk  ,  rst_n;
output    clk_out      ;

//=======================================================================\
//**************************Internal Signals******************************
//=======================================================================/

reg [3:0] cnt_p , cnt_n;  //clk上升沿（下降沿）触发生成的计数器cnt_p(cnt_n)
reg       clk_p , clk_n;  //clk上升沿（下降沿）触发生成的时钟clk_p(clk_n)

parameter N=5 ;          //分频参数


//===========================================================================\
//*****************************main code************************************
//==========================================================================/

//cnt_p 0-4
always @(posedge clk or negedge rst_n) begin
  if(!rst_n)
       cnt_p <= 4'd0;
  else if(cnt_p == N-1)
       cnt_p <= 0;
  else 
       cnt_p <= cnt_p + 1'b1;
  end

 //cnt_n  0-4
always @(negedge clk or negedge rst_n) begin 
  if(!rst_n)
       cnt_n <= 4'd0;
  else if(cnt_n == (N-1))
       cnt_n <= 0;
  else 
       cnt_n <= cnt_n + 1'b1;
  end
 
//clk_p 
always @(posedge clk or negedge rst_n) begin
  if(!rst_n)
      clk_p <= 1;
  else if(cnt_p == (N-1)/2-1) 
      clk_p <= ~clk_p;
  else if(cnt_p == (N-1))
      clk_p <= ~clk_p;
  end

//clk_p
always @(negedge clk or negedge rst_n) begin
  if(!rst_n)
      clk_n<=1;
  else if(cnt_n==(N-1)/2-1)
      clk_n<=~clk_n;
  else if(cnt_n==(N-1))
      clk_n<=~clk_n;
  end  
 assign clk_out=clk_n|clk_p;

 endmodule

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3. The half-integer divider

Half-integer division, the times to 2.5 frequency division as an example. This mainly using rising and falling edges of the clock counted.