Asynchronous reset synchronous release
When performing a timing analysis to ensure the transmission of signals to meet the setup and hold times, to avoid the occurrence of metastable sampling (metastable state will cause sampling uncertainty; metastable spread). Also reset signal when the reset and release must meet the setup and hold times. Generally use synchronous asynchronous reset release, as shown in FIG.
Left two registers are synchronized release register, the right is the need to reset the design.
1. When rst_async_n low, the reset time, asynchronous reset immediately design.
2. When rst_async_n from low to high, the reset is released when the first sampling stage register VCC metastability may occur, a resynchronization of the second stage, with virtually no metastability.
always @ (posedge clk, negedge rst_async_n)
if (!rst_async_n)
{rst_s2,rst_s1} <= 0;
else
{rst_s2,rst_s1} <= {rst_s1,1'b1};
assign rst_sync_n = rst_s2;
endmodule
Two basic synchronization can eliminate metastable
Release synchronization circuit, the first stage register typically occurs metastable, metastable propagation period of time (less than one cycle), can restore stability, the second stage register after sampling the signal is stable without occurrence of metastable . But if the process is very advanced when metastable lasted for more than one cycle, then the second stage register metastable sampling will occur, which will require the third pole synchronous register.
reference
https://blog.csdn.net/u011729865/article/details/49281713#commentBox