RTL design (8)-asynchronous reset and synchronous release

Synchronous reset, asynchronous reset

Synchronous reset: The reset signal is valid only when the rising edge of the clock arrives.
Advantages: (1) Because it is only valid when the clock effective level arrives, it can filter out burrs higher than the clock frequency; (2) The designed system can be a 100% synchronous sequential circuit, which is conducive to timing analysis.
Disadvantages: (1) The effective duration of the reset signal must be greater than the clock cycle in order to be truly recognized by the system and complete the reset task. At the same time, factors such as clk skew, combinatorial logic path delay, reset delay, etc. must be considered; (2) Since most of the DFFs in the target library of FPGA logic devices have only asynchronous reset ports, so if you use synchronous reset If so, the synthesizer will insert combinational logic into the data input port of the register, which will consume more logic resources.

Asynchronous reset: Regardless of the arrival of the clock edge, as long as the reset signal is valid, a reset is performed.
Advantages: (1) Fast response ; (2) Relatively simple design; (3) Because most DFFs of target device libraries have asynchronous reset ports, asynchronous reset can save resources.
Disadvantages: (1) The reset signal is easily affected by glitches. (2) Problems are prone to occur when the reset signal is released . Specifically, if the reset release happens to be near the valid edge of the clock, it is easy to cause the register output to appear metastable, resulting in a metastable state.

Asynchronous reset and synchronous release

In order to retain the advantages of the fast response of the asynchronous reset and avoid metastable state when the reset signal is released, an asynchronous reset synchronous release circuit is produced.
(Gate circuits can be used to form a glitch filter to reduce glitch interference.)

resetSynchronizer.v

`timescale 1ns / 1ps

// Company: 
// Engineer: 
// 
// Create Date: 2020/12/17
// Author Name: Sniper
// Module Name: resetSynchronizer
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module resetSynchronizer(
    input clk,
	input extern_rst_n,
    output system_rst_n
);

reg buff1;
reg buff2;

always@(posedge clk or negedge extern_rst_n)
    if(!extern_rst_n)
		buff1 <= 1'b0;
    else
		buff1 <= 1'b1;

always@(posedge clk or negedge extern_rst_n)
    if(!extern_rst_n)
		buff2 <= 1'b0;
    else
		buff2 <= buff1;


assign system_rst_n = buff2;


endmodule

tb_resetSynchronizer.v

`timescale 1ns / 1ps

// Company:
// Engineer:
//
// Create Date: 2020/12/17
// Author Name: Sniper
// Module Name: tb_resetSynchronizer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//


module tb_resetSynchronizer;

//input
reg clk;
reg extern_rst_n;


//output
wire system_rst_n;



initial
begin
    clk = 0;
    extern_rst_n = 0;

	#100;
    extern_rst_n = 1;

	#86;
    extern_rst_n = 0;
	#8;
    extern_rst_n = 1;

	#86;
    extern_rst_n = 0;
	#68;
    extern_rst_n = 1;

end

//clock
always #5 clk = ~clk;



//DUT
resetSynchronizer DUT
(
    .clk(clk),
    .extern_rst_n(extern_rst_n),
    .system_rst_n(system_rst_n)
);

initial
begin
    $dumpfile("tb_resetSynchronizer.vcd");
    $dumpvars(0,tb_resetSynchronizer);
end

initial #1000 $finish;

endmodule

Simulation results

vcs -R resetSynchronizer.v tb_resetSynchronizer.v

It can be found from the result that the release of system_rst_n is synchronized with clk and can be used as an asynchronous reset source signal inside the chip.