FPGA verilog warning: trap in reset

When writing the I2C interface, analysis and synthesis code today, a warning that has not been seen or rarely seen before appeared, here is a record:

Look at the code first:

//设备地址
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin
        device_addr_a <= {4'b1010,device_addr,1'b0};
    end
    else if(wr_flag) begin
        device_addr_a <= {4'b1010,device_addr,1'b0};
    end
    else if(rd_flag) begin
        device_addr_a <= {4'b1010,device_addr,1'b1};
    end
    else begin
        device_addr_a <= {4'b1010,device_addr,1'b0};
    end
end

caveat:

Warning (13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
    Warning (13310): Register "device_addr_a[2]" is converted into an equivalent circuit using register "device_addr_a[2]~_emulated" and latch "device_addr_a[2]~1"
    Warning (13310): Register "device_addr_a[1]" is converted into an equivalent circuit using register "device_addr_a[1]~_emulated" and latch "device_addr_a[1]~5"
    Warning (13310): Register "device_addr_a[3]" is converted into an equivalent circuit using register "device_addr_a[3]~_emulated" and latch "device_addr_a[3]~9"

In this warning, it roughly means that the preset and clearable register has been converted into an equivalent circuit with a latch.

It means that the latch is generated anyway, and everyone knows that in the fight, the latch should be avoided as much as possible in the FPGA design to prevent excessive resources from occupying the circuit stability.

the reason:

In the code, this signal is given to a specific register data when resetting. When the circuit is reset, the signal should be cleared to zero or preset to a certain constant.

solve:

Change the signal under reset to a certain value:

//设备地址
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin
        device_addr_a <= 0;
    end
    else if(wr_flag) begin
        device_addr_a <= {4'b1010,device_addr,1'b0};
    end
    else if(rd_flag) begin
        device_addr_a <= {4'b1010,device_addr,1'b1};
    end
    else begin
        device_addr_a <= {4'b1010,device_addr,1'b0};
    end
end

In this way, there will be no more errors in recompiling.