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1. Synchronous reset
Synchronous reset means that the reset signal is sampled only when the rising edge of the clock arrives, that is, the reset signal is valid only when the rising edge of the clock occurs.
Its RTL code is as follows:
2. Asynchronous reset
Asynchronous reset means that regardless of whether the clock edge comes, as long as the reset signal is valid, the system is reset. The RTL code is as follows:
3. Asynchronous reset and synchronous release
The so-called asynchronous reset and synchronous release means that when the reset signal arrives, it is not synchronized by the clock signal, but is synchronized by the clock signal when the reset signal is released.
As shown in the figure above, looking at the reset strategy of box 2 alone, it is an asynchronous reset circuit, that is, when the reset signal is valid, regardless of whether the clock signal is on the valid edge or not, the output will be reset, but if the reset signal is cancelled on the rising edge of the clock signal, this When the output is metastable.
The circuit diagram in block 1 is the key to realizing asynchronous reset and synchronous release.
First look at how to implement asynchronous reset: when rst_async_n is valid, the output rst_sync_n of the second D flip-flop is low, the asynchronous reset port in block 2 is valid, and the output is reset.
Then there is the synchronous release: assuming that rst_async_n is removed at the rising edge of clk, then the first-stage flip-flop is in a metastable state, but due to the buffering effect of the two-stage flip-flop, the input of the second-stage flip-flop is the first stage before the arrival of clk The output of the flip-flop is low. Therefore, the output of the second-stage flip-flop must be a stable low level at this time, and the flip-flop in block 2 is still in the reset state. When the next clk arrives, the output of the first-stage flip-flop is already a stable high level, so rst_sync_n is already a stable high level, and the reset is released at this time. That is, synchronous release.
Its implementation code is as follows:
This article is reproduced from http://blog.chinaaet.com/hu_li/p/5100052320 . If there is any infringement, please send a private message to the editor to delete it.
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