Various principles microcontroller reset circuit
Action reset circuit
On power-up or reset, the reset state of the CPU control: Let the CPU remains in the reset state during this time, rather than just a power-up or reset on completion of the work, to prevent the CPU sends the wrong instruction, execution error operation can be improved electromagnetic compatibility.
No matter what type of microcontroller users, always involves the design of the microcontroller reset circuit. The microcontroller reset circuit design directly affect the reliability of the whole system work. After many users in the SCM system design and debugging success in the laboratory, in the field but a "crash", "program to go fly," and so on, mainly single-chip reset circuit design caused by unreliable.
Basic Reset
Microcontrollers require a reset at startup, to cause the CPU and the system components identified in the initial state, and the work started from the initial state. MCU 89 from the reset signal RST is inputted to the Schmitt trigger pin in the chip. When the system is in normal operation, and after the oscillator has stabilized, and there is a high level for 2 machine cycles (24 oscillator periods) above, and the CPU can respond if the system reset RST pin. SCM system reset modes: manual reset button and power-on reset
1, the manual reset button
Manual reset button requires human added high level (FIG. 1) at the reset input terminal RST. Approach is generally used in an indirect and a button terminal RST of the positive power source Vcc. When the button is pressed man, the level of Vcc + 5V will be applied directly to terminal RST. Manual button reset circuit as shown in FIG. Since human movement and then quickly cause the button can be turned up to tens of milliseconds, can completely meet the requirements of the reset time.
2, the power-on reset
AT89C51 power-on reset circuit as shown, as long as the reset input RST in a capacitor connected to the Vcc terminal pins, then under a resistor to ground to 2. For the single-chip CMOS, since the inner end of a pull-down resistor RST, an external resistor may be removed so that, while the reduced external capacitor 1μF. The working process is reset upon power up, reset circuit via a capacitor terminal RST applied to a short high-level signal, with this high-level signal Vcc and the charging process of the capacitor gradually decline, i.e., a high electric terminal RST the duration depends on the flat capacitor charging time. In order to ensure that the system can reliably reset, RST terminal of a high level signal must be maintained for a sufficient period of time. On power, Vcc rise time is about 10ms, and the oscillator start-up time depends on the oscillation frequency, as the crystal frequency is 10MHz, the start-up time is 1ms; crystal frequency is 1MHz, start-up time was 10ms. In the reset circuit of FIG. 2, when the power-down Vcc, RST is bound to make the terminal voltage rapidly drops to 0V or less, however, due to the limiting effect of the internal circuit, the negative voltage does not cause damage to the device. Further, during reset, the port pins are in a random state, after reset, the port will be set to all "l" state. If the system can not be effectively reset at power on, the program counter PC will not be a suitable initial value, therefore, the CPU executes the program may start from a position not defined.
3, the integral reset
Conventional switching power-up or reset circuit shown in Figure 3. After power-up, due to charge capacitor C3 and the inverting gate, so that the high level period of duration RST. When the microcontroller is already running which, after pressing the reset key K release, also allows a high level period RST, to achieve power-up or reset switch operation.
Capacitor experience the actual operation, this reset circuit is given below, the reference resistance value.
FIG 3: C: = 1uF, Rl = lk, R2 = 10k
FIG 3 integral on reset circuit
ASIC reset circuit:
Acting on reset circuit in the control system is to start the microcontroller to begin work. However, at power and voltage anomalies or interference in normal operation, there will be some instability in the power factor for the stability of the microcontroller could have serious repercussions. Thus, a delay output to the chip output the reset signal when the power supply. Another function of the reset circuit is that the power supply voltage during normal operation *. When the power supply abnormality will be forced reset. Reset output requires continuous three pin output low (12 / fc s) or more instruction cycle, the reset procedure begins initial internal state of the chip initialization. Waiting to receive an input signal (if the signal such as a remote controller, etc.).
On reset circuit of FIG 4 Schematic
Analysis on reset circuit principle
5V power supply through MC34064 input pin 2, pin 1 can output a positive edge triggered reset pin chip. Electrolytic capacitor C13 is adjusting the delay time of the reset. When the power is turned off, the residual charge on the electrolytic capacitor C13 and D13 constitute a loop through the internal circuit MC34064, freed charge. To prepare for the next reset is enabled. (F * |, ^ (P | 9 O) Z3 i
Fourth, the key-on reset circuit device
There are key devices: MC34064.
6 a block diagram showing the internal structure of FIG.
Input-output characteristic curve:
Power-on reset circuit electrical parameters of key points
MC34064 output pin 1 output pin (output after stabilization) as shown below:
Transistor brown-out circuit
BOR circuit works (FIG. 6) w is powered, + 5V rises from the voltage "0V", before the rise 3.6V, the zener diode DH03 are in the OFF state, QH01 (PNP pipe) is also in an off state , no reset voltage is output. When w + 5V power supply voltage is higher than 3.6V after, DH03 reverse breakdown zener diode, the voltage across the "clamped" to 3.6V. When the + 5V power supply voltage is higher than 4.3V, QH01 begins to conduct, the reset voltage begins to form, when the + 5V power supply voltage close to + 5V, QH01 saturated conduction, the reset voltage reaches a steady state.
6 a circuit diagram of FIG BOR
Type watchdog reset circuit
看门狗型复位电路主要利用CPU正常工作时,定时复位计数器,使得计数器的值不超过某一值;当CPU不能正常工作时,由于计数器不能被复位,因此其计数会超过某一值,从而产生复位脉冲,使得CPU恢复正常工作状态。典型应用的Watchdog复位电路如图7所示。此复位电路的可靠性主要取决于软件设计,即将定时向复位电路发出脉冲的程序放在何处。一般设计,将此段程序放在定时器中断服务子程序中。然而,有时这种设计仍然会引起程序走飞或工作不正常。原因主要是：当程序“走飞”发生时定时器初始化以及开中断之后的话,这种“走飞”情况就有可能不能由Watchdog复位电路校正回来。因为定时器中断一真在产生,即使程序不正常,Watchdog也能被正常复位。为此提出定时器加预设的设计方法。即在初始化时压入堆栈一个地址,在此地址内执行的是一条关中断和一条死循环语句。在所有不被程序代码占用的地址尽可能地用子程序返回指令RET代替。这样,当程序走飞后,其进入陷阱的可能性将大大增加。而一旦进入陷阱,定时器停止工作并且关闭中断,从而使Watchdog复位电路会产生一个复位脉冲将CPU复位。当然这种技术用于实时性较强的控制或处理软件中有一定的困难
图7 看门狗型复位电路
比较器型复位电路
比较器型复位电路的基本原理如图8所示。上电复位时,由于组成了一个RC低通网络,所以比较器的正相输入端的电压比负相端输入电压延迟一定时间。而比较器的负相端网络的时间常数远远小于正相端RC网络的时间常数,因此在正端电压还没有超过负端电压时,比较器输出低电平,经反相器后产生高电平。复位脉冲的宽度主要取决于正常电压上升的速度。由于负端电压放电回路时间常数较大,因此对电源电压的波动不敏感。但是容易产生以下二种不利现象：(1)电源二次开关间隔太短时,复位不可靠;(2)当电源电压中有浪涌现象时,可能在浪涌消失后不能产生复位脉冲。为此,将改进比较器重定电路,如图9所示。这个改进电路可以消除第一种现象,并减少第二种现象的产生。为了彻底消除这二种现象,可以利用数字逻辑的方法与比较器配合,设计如图9所示的比较器重定电路。此电路稍加改进即可作为上电复位与看门狗复位电路共同复位的电路,大大提高了复位的可靠性。
图8 比较器型复位电路
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